A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS

Abstract

A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.