{"title":"具有接收端PWM(时域)前馈均衡的PAM-8有线收发器，在65nm CMOS中工作范围为12至39.6 gb /s","authors":"Yusang Chun, Ashwin Ramachandran, Tejasvi Anand","doi":"10.1109/ESSCIRC.2019.8902575","DOIUrl":null,"url":null,"abstract":"A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS\",\"authors\":\"Yusang Chun, Ashwin Ramachandran, Tejasvi Anand\",\"doi\":\"10.1109/ESSCIRC.2019.8902575\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902575\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS
A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.
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