Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)最新文献

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FPGA Implementation of an Artificial Neural Network for Subatomic Physics Experiment Particles Recognition 亚原子物理实验粒子识别人工神经网络的FPGA实现
Ruiguang Zhao, A. Besson, C. Hu-Guo, Luis Alejandro Perez perez, K. Jaaskelainen, M. Goffe, Yann Hu
{"title":"FPGA Implementation of an Artificial Neural Network for Subatomic Physics Experiment Particles Recognition","authors":"Ruiguang Zhao, A. Besson, C. Hu-Guo, Luis Alejandro Perez perez, K. Jaaskelainen, M. Goffe, Yann Hu","doi":"10.22323/1.343.0066","DOIUrl":"https://doi.org/10.22323/1.343.0066","url":null,"abstract":"CMOS Pixel Sensors have been used in subatomic physics experiments for charged particles detection. In the International Linear Collider (ILC) vertex detector, the occupancy will be mainly driven by impacts coming from the beam background. This will have a huge impact to the data flow of the system. We propose a design of CMOS pixel sensors with on-chip Artificial Neural Network (ANN) to tag and remove these hits. It is based on different features of hits clusters. In this paper, we will describe the structure of an ANN implemented in an FPGA device. We will show and analyze the distribution of incident angles reconstructed by the ANN.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1 GS/s sampling digitizer designed with interleaved architecture (GSPS) for the LaBr3 detectors of the FAMU experiment 为FAMU实验LaBr3探测器设计了一种采用交错结构(GSPS)的1gs /s采样数字化仪
R. Travaglini, G. Baldazzi, I. D'Antone, S. Meneghini, L. Rignanese, M. Zuffa
{"title":"A 1 GS/s sampling digitizer designed with interleaved architecture (GSPS) for the LaBr3 detectors of the FAMU experiment","authors":"R. Travaglini, G. Baldazzi, I. D'Antone, S. Meneghini, L. Rignanese, M. Zuffa","doi":"10.22323/1.343.0022","DOIUrl":"https://doi.org/10.22323/1.343.0022","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123934970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Control and Monitoring for a serially powered pixel demonstrator for the ATLAS Phase II upgrade ATLAS第二阶段升级的串行供电像素演示器的控制和监控
N. Lehmann
{"title":"Control and Monitoring for a serially powered pixel demonstrator for the ATLAS Phase II upgrade","authors":"N. Lehmann","doi":"10.22323/1.343.0133","DOIUrl":"https://doi.org/10.22323/1.343.0133","url":null,"abstract":"The Inner Tracker (ITk) is a new, all-silicon detector under development for the ATLAS Phase-II upgrade and will operate at the High Luminosity LHC. A serial power (SP) scheme will be used for the ITk Pixel Detector. New elements are required to operate and monitor a serially powered detector, including a Detector Control System (DCS), constant current sources and front-end electronics with shunt regulators. A demonstrator for the three outer barrel layers of the ITk Pixel Detector is being built at CERN to verify and qualify the SP concept, and to gain experience operating a SP chain. It includes all required elements for controlling and operating SP chains safely, from an interlock system to in-situ monitoring with a new DCS. A first full electrical prototype with seven quad modules was successfully tested. This prototype includes pixel modules, the DCS elements, realistic services and can be read out by different data acquisition systems. Problems identified during the commissioning and operation of the small electrical prototype went into the requirements for the future front-end (FE) chips. Many institutes worked on the development and integration of the individual parts. Further and longer chains are under construction and will allow tests of multiple SP chains mounted on the same local support in parallel. It is also foreseen to operate a SP chain with 16 modules.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128728371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
New development in the CMS ECAL Level-1 trigger system to meet the challenges of LHC Run 2 CMS ECAL一级触发系统的新发展,以应对LHC运行2的挑战
F. Thiant, Y. Geerebaert, F. Magniette, T. Romanteau, A. Zabi, A. Zghiche
{"title":"New development in the CMS ECAL Level-1 trigger system to meet the challenges of LHC Run 2","authors":"F. Thiant, Y. Geerebaert, F. Magniette, T. Romanteau, A. Zabi, A. Zghiche","doi":"10.22323/1.343.0052","DOIUrl":"https://doi.org/10.22323/1.343.0052","url":null,"abstract":"The CMS Electromagnetic Calorimeter (ECAL) provides energy sums to the Level-1 Calorimeter Trigger at a rate of 40 MHz. The processing of these trigger primitives (TPs) is performed by dedicated trigger concentrator cards (TCCs) located in the CMS service cavern. Updates to the functionality of the TCCs were required to respond to the challenging experimental conditions of LHC Run 2, where the center-of-mass of proton-proton collision energy was 13 TeV and the peak instantaneous luminosity of the proton beams reached 2x1034 cm-2 s-1. A new algorithm, termed the Cumulative Overflow Killing Engine (COKE), has been developed and implemented via software and firmware updates to the TCCs in order to automatically detect and mask noisy or problematic TPs via configurable thresholds. The autorecovery of the TCCs has also been improved, to manage the Single Event Upsets (SEUs) from the front-end electronics. This allows the detector to trigger efficiently without direct expert intervention, and the thresholds can evolve with evolving LHC conditions. Topical Workshop on Electronics for Particle Physics (TWEPP2018) 17-21 September 2018 Antwerp, Belgium","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ATLAS Tile Calorimeter Link Daughterboard ATLAS瓷砖量热计链接子板
E. Santurio, S. Silverstein, C. Bohm
{"title":"ATLAS Tile Calorimeter Link Daughterboard","authors":"E. Santurio, S. Silverstein, C. Bohm","doi":"10.22323/1.343.0024","DOIUrl":"https://doi.org/10.22323/1.343.0024","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127302129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ethernet-based slow control system for parallel configuration of FPGA-based front-end boards 基于以太网的慢速控制系统并行配置基于fpga的前端板
Wojciech Zabolotny
{"title":"Ethernet-based slow control system for parallel configuration of FPGA-based front-end boards","authors":"Wojciech Zabolotny","doi":"10.22323/1.343.0068","DOIUrl":"https://doi.org/10.22323/1.343.0068","url":null,"abstract":"The Ethernet network is a good control interface for distributed measurement systems. The de facto standard in HEP experiments is IPbus. The experiences from using IPbus resulted in the proposal of a new Ethernet-based control interface optimized for quick parallel configuration of multiple systems. The system ensures reliable delivery of control commands and responses. The adverse effects of the Ethernet round-trip latency are minimized by grouping the multiple commands in a single network packet, including the basic handshake operations like waiting with timeout until a specified condition is met. The performance may be increased by using multiple packets “in flight”. Usage of Layer 2 Ethernet frames minimizes the FPGA resource consumption. Implementation of the software part in Linux kernel space reduces dependency on specific software packages and libraries.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128220578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis 一种用于时间-数字转换器的低迟滞、快速恢复的延时锁环
B. Van Bockel, J. Prinzie, Ying Coa, P. Leroux
{"title":"A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis","authors":"B. Van Bockel, J. Prinzie, Ying Coa, P. Leroux","doi":"10.22323/1.343.0027","DOIUrl":"https://doi.org/10.22323/1.343.0027","url":null,"abstract":"This paper proposes the simulation results of a 1 GHz Delay Locked Loop (DLL) designed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. A novel phase detector consisting of an improved bang-bang phase detector and a 3state controller was introduced, leading to a a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter, and achieves an in lock hysteresis of only 500 fs.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigations into the effect of gamma irradiation on the leakage current of 130-nm readout chips for the ATLAS ITk strip detector 辐照对ATLAS ITk条探测器130 nm读出芯片漏电流影响的研究
R. Wölker, C. Sawyer, Atlas ITk Community
{"title":"Investigations into the effect of gamma irradiation on the leakage current of 130-nm readout chips for the ATLAS ITk strip detector","authors":"R. Wölker, C. Sawyer, Atlas ITk Community","doi":"10.22323/1.343.0121","DOIUrl":"https://doi.org/10.22323/1.343.0121","url":null,"abstract":"Central to the design of any detector system is a detailed understanding of the current and power dissipation due to the implications on power-supply design, thermal management and mechanical stability. It is well documented that certain 130-nm CMOS technologies exhibit an increase in the leakage current when exposed to ionising radiation. Such 130-nm technology is employed in the readout ASICs of the ATLAS ITk Strip Tracker Upgrade. Using the so-called ABC130 prototype chipset, measurements are presented which allow the parametrisation of the increase in current as a function of dose rate in the region of phase space most applicable to High-Luminosity LHC conditions. Studies investigating the batch-by-batch, chip-by-chip and wafer-by-wafer variation of the total current increase are presented which demonstrate a significant batch-by-batch variation alongside non-negligible variations within wafers. Furthermore, studies are shown investigating the long-term annealing of irradiated chips (up to four months storing chips at 80 C). Finally, the feasibility of pre-irradiating wafers to mitigate the current increase is demonstrated.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115313238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation 一种用于逐次逼近的电荷再分配模数转换器的电容DAC
P. Vancura, M. Havranek, T. Benka, Z. Janoška, J. Jakovenko, V. Vrba
{"title":"A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation","authors":"P. Vancura, M. Havranek, T. Benka, Z. Janoška, J. Jakovenko, V. Vrba","doi":"10.22323/1.343.0094","DOIUrl":"https://doi.org/10.22323/1.343.0094","url":null,"abstract":"The recent analog to digital converters, with the successive approximation (SAR ADC), are widely used for their high speed, low power operation and accuracy. SAR ADC demands precise internal digital to analog converter (DAC). To save power, the DAC is mainly implemented using capacitors (CDAC). Its precision depends mostly on layout implementation which must minimize the various parasitic effects. This paper presents two new layout design approaches of CDAC for SAR ADC used in a pixel detector implemented in 180 nm SOI technology. The various types, topology, size of the capacitors, power consumption, layout area, speed, and any nonlinearities are discussed. First is a new layout design of the 10-bit split capacitor DAC with \u0000Metal-Insulator-Metal capacitors, and, the second, is a 8-bit binary-weighted DAC with Metal-Oxide-Metal capacitors. The new layout of the metal-oxide-metal capacitor topology provides better accuracy of the DAC. The layout styles for each of CDAC, with low parasitic capacitances, are shown. The post layout simulations confirm that both capacitor arrays have an integral, differential nonlinearity, less than one least significant bit without a calibration scheme.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of the monolithic "MALTA" CMOS sensor for the ATLAS ITK outer pixel layer ATLAS ITK外像素层单片“MALTA”CMOS传感器的研制
B. Hiti, Lluis Simon Argemi, I. Tortajada, I. Berdalovic, I. C. Sierra, R. Cardella, F. Dachs, V. Dao, Nuria Egidos Plaja, A. Gorišek, T. Hemperek, H. Krüger, T. Kugathasan, I. Mandić, C. A. M. Tobon, K. Moustakas, M. Munker, H. Pernegger, F. Piro, P. Riedler, P. Rymaszewski, C. Riegel, E. J. Schioppa, Abhishek Sharma, W. Snoeys, C. S. Sánchez, T. Wang, Wermes Norbert
{"title":"Development of the monolithic \"MALTA\" CMOS sensor for the ATLAS ITK outer pixel layer","authors":"B. Hiti, Lluis Simon Argemi, I. Tortajada, I. Berdalovic, I. C. Sierra, R. Cardella, F. Dachs, V. Dao, Nuria Egidos Plaja, A. Gorišek, T. Hemperek, H. Krüger, T. Kugathasan, I. Mandić, C. A. M. Tobon, K. Moustakas, M. Munker, H. Pernegger, F. Piro, P. Riedler, P. Rymaszewski, C. Riegel, E. J. Schioppa, Abhishek Sharma, W. Snoeys, C. S. Sánchez, T. Wang, Wermes Norbert","doi":"10.22323/1.343.0155","DOIUrl":"https://doi.org/10.22323/1.343.0155","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126562342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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