Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)最新文献

{"title":"A High Dynamic Range ASIC for Time of Flight PET with monolithic crystals","authors":"S. G. Fernández, A. Sanmukh, D. Gascón, D. Sánchez, J. Mauricio, R. Graciani, R. Manera, L. Garrido, L. Freixes, J. Marín, O. Vela, José M. Fernández, J. Cela, J. Navarrete, J. Oller, J. Pérez, P. Rato","doi":"10.22323/1.343.0085","DOIUrl":"https://doi.org/10.22323/1.343.0085","url":null,"abstract":"The HRFlexToT is a 16-channel ASIC for SiPM anode readout designed for Positron Emission Tomography (PET) applications that features high dynamic range (>8 bits), low input impedance, common cathode connection, high speed and low power (~3.5 mW/ch). The ASIC has been manufactured using XFAB 0.18 mm CMOS technology. The main characteristics of the HRFlexToT, compared to its predecessor, are a new energy measurement readout providing a linear Time Over Threshold (ToT) with an extended dynamic range, lower power consumption and better timing response. Initial measurements show a linearity error below 3%. Single Photon Time Resolution (SPTR) measurements performed using a Hamamatsu MPPC S13360-3050CS (3x3 mm2 pixel, 50 umm cell) shows 30% improvement with respect to the previous version of the ASIC, setting this specification in the order of 141 ps FWHM and reducing 3 times power consumption. It is important to highlight that an SPTR of 141 ps FWHM is, according to the best of our knowledge, the best resolution achieved so far for this sensor. Coincidence Time Resolution (CTR) measurements are expected to be performed during 2018.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114439980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Ultra-Fast 10Gb/s 64b66b Data Serialiser Backend in 65nm CMOS Technology","authors":"T. Gardiner","doi":"10.22323/1.343.0088","DOIUrl":"https://doi.org/10.22323/1.343.0088","url":null,"abstract":"With future pixel ASICs trending towards mega-frame rate readout, the development of ultrahigh-speed readout systems is increasingly important. Here we present an ultra-fast readout \u0000system developed to operate at 10Gbps, and intended to surpass a more conventional highlyparallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles \u0000and serialises the parallel input data in accordance with the Aurora 64b66b protocol, and \u0000transmits the data off-chip through a Current Mode Logic (CML) line-driver at 10Gbps. A \u0000prototype is under evaluation having been fabricated in early 2018 on a 65nm Multi-Project \u0000Wafer. Serialiser ASIC ran at 10.312Gbps under test for 60 hours without a bit-error event.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ALICE trigger system for LHC Run 3","authors":"M. Krivda, D. Evans, A. Jusko, J. Kvapil, R. Lietava, O. Baillie, E. Willsher, I. Králik, M. Bombara, L. Tropp, L. Moreno","doi":"10.22323/1.343.0119","DOIUrl":"https://doi.org/10.22323/1.343.0119","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131202337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First Double-Sided End-Cap Strip Module for the ATLAS High-Luminosity Upgrade","authors":"L. Wiik-Fuchs, U. Parzefal, C. G. Argos, M. Hauser, K. Jakobs, K. Mahboubi, Arturo Rodriguez, F. Ruehr, V. Prahl, Dario Eliecer Arziza Alvarez, I. Bloch, S. D. Cornell, I. Gregor","doi":"10.22323/1.343.0015","DOIUrl":"https://doi.org/10.22323/1.343.0015","url":null,"abstract":"• First double sided end-cap module successfully built and tested • Assembly procedure well understood • Simultaneous readout of both sides • Generally expected electrical performance • Slight noise increase observed on one side, attributed to sensor breakdown issues • Further characterisation of the module in beam test Petal with 9 sensors End-cap layout: 6 discs with 32 petals each, in global support structure Inner Tracker Layout: barrel and endcap, showing pixel and strip systems","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129364036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability test results of the interconnect structures of the front-end hybrids for the CMS Phase-2 Tracker Upgrade","authors":"M. Kovács, R. Gajanec, B. Allongue, G. Blanchot, T. Gądek, F. André","doi":"10.22323/1.343.0146","DOIUrl":"https://doi.org/10.22323/1.343.0146","url":null,"abstract":"High Density Interconnect (HDI) hybrids are being developed for the CMS Tracker Phase Two Upgrade for the HL-LHC. These hybrids are carbon fibre reinforced flexible circuits with flip-chips, passives and connectors. Their operational lifetime is determined by the reliability of the solder joints of the surface mount components (flip-chips, passives, connectors) and the copper traces and vias in the hybrid substrate. Specific test coupons were exposed to accelerated thermal stress cycles, aiming to test the reliability of the solder joints, vias and traces. Results from different suppliers and technologies will be evaluated and compared. Topical Workshop on Electronics for Particle Physics 17 21 September 2018 Antwerp, Belgium","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of the MPA prototype, a 65 nm pixel readout ASIC with on-chip quick transverse momentum discrimination capabilities.","authors":"D. Ceresa, M. Haranko, K. Kloukinas, J. Kapłon, Alessandro Caratelli, D. Giovinazzo, J. Murdzek, S. Scarfi, J. Clercq","doi":"10.22323/1.343.0166","DOIUrl":"https://doi.org/10.22323/1.343.0166","url":null,"abstract":"The first prototype of the full-size, full-functionality Macro Pixel ASIC has been produced in a 65 nm technology employing radiation tolerant techniques. It is a pixel readout ASIC designed for the Phase2 upgrade of the CMS Outer Tracker detector. It features novel on-chip particle discrimination capabilities allowing for real-time event-driven readout of high transverse momentum particles at a 40 MHz rate. This data flow is complemented with a zero suppressed triggered readout data path for the readout of full events at a maximum rate of 1 MHz. This contribution presents the functional and performance evaluation results obtained from silicon prototypes. Presented at TWEPP2018 Topical Workshop on Electronics for Particle Physics Characterization of the MPA prototype, a 65 nm pixel readout ASIC with on-chip quick transverse momentum discrimination capabilities. Davide Ceresa*a†, Alessandro Caratelliab†, Jarne Theo De Clercqc, Dena Giovinazzod , Mykyta Harankoe, Jan Kaplona, Kostas Kloukinasa, Jan Murdzeka, Simone Scarfìab on behalf of the CMS Tracker Group. a European Organization for Nuclear Research (CERN), Geneva, Switzerland. b Microelectronic System Laboratory (LSM), École polytechnique fédérale de Lausanne (EPFL), Lausanne, Switzerland. c Vrije Universiteit Brussel, Brussel, Belgium. d UCSC, Santa Cruz, California, USA. e Deutsches Elektronen-Synchrotron, Hamburg, Germany. E-mail: Davide.Ceresa@cern.ch, Alessandro.Caratelli@epfl.ch The first prototype of the full-size, full-functionality Macro Pixel ASIC has been produced in a 65 nm technology employing radiation tolerant techniques. It is a pixel readout ASIC designed for the Phase-2 upgrade of the CMS Outer Tracker detector. It features novel on-chip particle discrimination capabilities allowing for real-time event-driven readout of high transverse momentum particles at a 40 MHz rate. This data flow is complemented with a zero suppressed triggered readout data path for the readout of full events at a maximum rate of 1 MHz. This contribution presents the functional and performance evaluation results obtained from silicon prototypes. Topical Workshop on Electronics for Particle Physics 17 21 September 2018, KU Leuven Campus Carolus, Antwerpen, Belgium *Speaker. †Main authors © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0). https://pos.sissa.it/ Characterization of the MPA prototype Davide Ceresa","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A System-Verilog Verification Environment for the CIC Data Concentrator ASIC of the CMS Outer Tracker Phase-2 Upgrades","authors":"S. Scarfi, K. Kloukinas, G. Galbit, S. Viret, D. Ceresa, L. Caponetto, Y. Leblebici, B. Nodari, Alessandro Caratelli","doi":"10.22323/1.343.0097","DOIUrl":"https://doi.org/10.22323/1.343.0097","url":null,"abstract":"The foreseen Phase-2 upgrades at the LHC present very challenging requirements for the front-end readout electronics of the CMS Outer Tracker detector. High data rates in combination with the employment of a novel technique for rejecting locally low transverse momentum particles as well as the strict low power consumption constraints require the implementation of an optimized readout architecture and specific interconnect synchronization schemes for its components. \u0000This work focuses on the development and the verification of the Concentrator IC (CIC) ASIC, a 65 nm digital chip featuring high input and output data rates, in the context of the readout chains incorporating all front-end ASICs: namely the Macro Pixel ASIC (MPA), Short Strip ASIC (SSA) for the Pixel-Strip (PS) modules and the CMS Binary Chip (CBC) for Strip-Strip (2S) Modules. The CIC ASIC receives high data rate (320 MHz) digital streams from eight Front-end ASICs via a total of 48 differential lines and transmits them through seven differential lines operating at 320 MHz or 640 MHz, depending on the occupancy of the detector module. \u0000A complex system level simulation environment based on the System-Verilog hardware description language and on the Universal Verification Methodology (UVM) platform has been adapted and extended to help the CIC development and verification simulating the complete readout chains from the particle event to the output of the modules. \u0000The paper is composed of four sections: the first one describes the pT module concept, the second presents the UVM environment for MPA/SSA ASICs adapted and extended to include the CIC, the third one shows the readout-chain forecasted performances and show some examples of usage of this framework. The last section presents the PS module efficiency as a function of the stub occupancy for different CIC output frequencies.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A collaborative HDL management tool for ATLAS L1Calo upgrades","authors":"F. Gonnella","doi":"10.22323/1.343.0142","DOIUrl":"https://doi.org/10.22323/1.343.0142","url":null,"abstract":"Coordinating firmware development among many international collaborators is becoming a very widespread problem in particle physics. Guaranteeing firmware synthesis with place and route (P&R) reproducibility and assuring traceability of binary files is of paramount importance. Our HDL managing tool, developed in Python and tightly integrated with CERN Gitlab and Xilinx Vivado, tackles these issues by exploiting advanced Git features and by paying particular attention to Intellectual Property handling. In LHC Run-3, the ATLAS L1Calo Trigger system will be upgraded with new feature extraction and readout modules and our tool is used for the firmware development for these modules.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116159173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The CMS Level-1 muon trigger for the LHC Run II","authors":"J. Heikkilae","doi":"10.22323/1.343.0049","DOIUrl":"https://doi.org/10.22323/1.343.0049","url":null,"abstract":"The CMS experiment uses a sophisticated two-level triggering system composed of hardware-based Level-1 Trigger, and a software-based High Level Trigger to select 1 kHz of events out of 40 MHz for later analysis. A new Level-1 trigger architecture improves the data taking performance at high luminosity experienced during Run II. The upgraded muon trigger increases the redundancy of the three muon detectors Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC) by combining information in the muon track finders with new track reconstruction, which yields a better efficiency and lower rates. The upgraded muon trigger system and the algorithms designed to select events for both precision measurements and new physics searches are described. The performance of the upgraded muon trigger system is demonstrated using proton-proton collision data collected in Run II. Presented at TWEPP2018 Topical Workshop on Electronics for Particle Physics The CMS Level-1 muon trigger for the LHC Run II Jaana Heikkilä∗ on behalf of the CMS Collaboration Helsinki Institute of Physics E-mail: jaana.heikkila@cern.ch The CMS experiment uses a sophisticated two-level triggering system composed of hardwarebased Level-1 Trigger, and a software-based High Level Trigger to select 1 kHz of events out of 40 MHz for later analysis. A new Level-1 trigger architecture improves the data taking performance at high luminosity experienced during Run II. The upgraded muon trigger increases the redundancy of the three muon detectors Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC) by combining information in the muon track finders with new track reconstruction, which yields a better efficiency and lower rates. The upgraded muon trigger system and the algorithms designed to select events for both precision measurements and new physics searches are described. The performance of the upgraded muon trigger system is demonstrated using proton-proton collision data collected in Run II. Topical Workshop on Electronics for Particle Physics 17-21 September 2018 Antwerp, Belgium","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126182470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Upgrade of the CMS Barrel Muon Track Finder for HL-LHC featuring a Kalman Filter algorithm and an ATCA Host Processor with Ultrascale+ FPGAs","authors":"C. Foudas, P. Katsoulis, T. Lama, S. Mallios, G. Karathanasis, I. Papavergou, S. Regnard, M. Tepper, P. Sphicas, Constantinos Vellidis, G. Karathanasis, M. Bachtis","doi":"10.22323/1.343.0139","DOIUrl":"https://doi.org/10.22323/1.343.0139","url":null,"abstract":"The Barrel Muon Track finder of the CMS experiment at the Large Hadron Collider uses custom \u0000processors to identify muons and measure their momenta in the central region of the CMS detector. An upgrade of the L1 tracking algorithm is presented, featuring a Kalman Filter in FPGAs, \u0000implemented using High Level Synthesis tools. The matrix operations are mapped to the DSP \u0000cores reducing resource utilization to a level that allows the new algorithm to fit in the same \u0000FPGA as the legacy one, thus enabling studies during nominal CMS data taking. The algorithm \u0000performance has been verified in CMS collisions during 2018 operations. The algorithm is also \u0000proposed for standalone muon tracking at the High Luminosity LHC. The algorithm development \u0000is complemented by ATCA processor R&D featuring a large ZYNQ Ultrascale+ SoC with high \u0000speed optical links.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132867724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}