Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)最新文献

{"title":"Serenity: An ATCA prototyping platform for CMS Phase-2","authors":"A. Rose, D. Parker, G. Iles, O. Sahin, P. Bausson, A. Tsirou, G. Fedi, P. Verdini, Luis Ardilla, M. Balzer, Thomas Schuh, T. Williams, A. Thea, K. Harder, S. Dugad, Raghunandan Shukla, I. Mirza","doi":"10.22323/1.343.0115","DOIUrl":"https://doi.org/10.22323/1.343.0115","url":null,"abstract":"Serenity is an ATCA prototyping platform designed to explore alternative, novel design choices \u0000for CMS Phase-2. It uses a newly available interconnect technology from Samtec (Z-RAY) to \u0000mount a removable processing unit (FPGA) that should mitigate risk and provides significant \u0000flexibility in processing unit choice and connectivity. We explore the pros and cons of using an \u0000industry-standard Computer-On-Module running standard Centos Linux and a small service \u0000FPGA for low level control. Specially designed Kapton heaters have been used to validate the \u0000thermal design of the card and broader considerations of ATCA systems.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation hard Depleted Monolithic Active Pixel Sensors with high-resistivity substrates","authors":"S. Terzo, M. Benoit, E. Cavallaro, R. Casanova, F. Foerster, S. Grinstein, G. Iacobucci, I. Perić, C. Puigdengoles, E. Vilella","doi":"10.22323/1.343.0125","DOIUrl":"https://doi.org/10.22323/1.343.0125","url":null,"abstract":"High Voltage/High resistivity Depleted Monolithic Active Pixel Sensors (HV/HR-DMAPS) is a technology which is becoming of great interest for high energy physics applications. \u0000With respect to hybrid pixel detectors the monolithic approach offers the main advantages of reduced material budget and production costs due to the absence of the bump bonding process. This aspect is important especially when large areas need to be covered as in the tracking detectors of the LHC experiments. Thus, the possibility of employing this technology in the outermost layers of the upgraded ATLAS pixel detector at the HL-LHC is being investigated. \u0000Different HR/HV-DMAPS prototypes have been recently developed for the future ATLAS Inner Tracker (ITk) with the aim of studying their radiation hardness and the feasibility of producing large area devices. \u0000 \u0000The H35DEMO is a large area demonstrator chip for the ITk designed by KIT, IFAE and University of Liverpool and produced in AMS 350 nm HV-CMOS technology with an engineering run on four different substrate resistivities: 20, 80, 200 and 1000 $mathrm{Omega cm}$. It consists of four large matrices, two of which include digital electronics and are thus fully monolithic. \u0000One, called CMOS matrix, has comparators made of CMOS transistors in the periphery only, while the other, called NMOS matrix, includes also comparators made of NMOS transistors directly in the pixels. The other two matrices have only analog front-end electronics and are meant to be coupled to ATLAS FE-I4 chips. \u0000All matrices feature pixels with a size of $mathrm{(50times250);mu m^2}$ in which the analog electronics are embedded in a Deep N-WELL (DNWELL) also acting as collecting electrode. \u0000A Data Acquisition (DAQ) system was developed at IFAE to read out and test the monolithic matrices of the H35DEMO both in the laboratory and with beam test experiments. \u0000H35DEMO chips with a resistivity of 200 $mathrm{Omega cm}$ have been irradiated with reactor neutrons to a particle fluence of $1times10^{15}$ $mathrm{1;MeV;n_{eq}/cm^2}$, the expected fluence for the outermost pixel layer of ITk. The monolithic CMOS matrix of the H35DEMO chip was extensively characterised before and after irradiation in beam tests at Fermilab and DESY, with proton and electron beams, respectively. \u0000Results after irradiation show good performance in terms of hit efficiency with thresholds of about 1800 e and a bias voltage of 150 V. \u0000 \u0000Another production of monolithic HV-CMOS prototypes in LFoundry 150 nm technology (LF2) has been recently completed. It includes sensors with a similar DNWELL concept as the H35DEMO but with a smaller pixel size of $mathrm{(50times50);mu m^2}$. Preliminary measurements of leakage current of the LF2 chips have been preformed showing good agreement with what expected from the foundry process.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133643359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Lightweight First-Level Muon Track Trigger for Future Hadron Collider Experiments","authors":"D. Cieri, S. Abovyan, V. Danielyan, M. Fras, P. Gadow, O. Kortner, S. Kortner, H. Kroha, F. Müller, S. Nowak, P. Richter, K. Schmidt-Sommerfeld","doi":"10.22323/1.343.0051","DOIUrl":"https://doi.org/10.22323/1.343.0051","url":null,"abstract":"Single muon triggers are crucial for the physics programmes at hadron collider experiments. To \u0000keep the trigger rates reasonably low they must be highly selective. \u0000Muon systems at LHC experiments and at future colliders use two muon chamber system for \u0000triggering: fast trigger chambers to identify the bunch crossing and provide a coarse momentum \u0000estimation, and slower precision chambers, for precise measurements of the muon trajectory. \u0000A fast lightweight track finding algorithm, based on the Hough Transform and Linear Regression \u0000techniques, has been designed and implemented on a Zynq SoC device, reconstructing successfully muon tracks in a single trigger sector.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prototype Front-end ASIC for Silicon-strip Detectors of J-PARC Muon g-2/EDM Experiment","authors":"Y. Tsutsumi, T. Kishishita, Yutaro Sato, M. Shoji, Manobu M. Tanaka, T. Mibe, J. Tojo","doi":"10.22323/1.343.0090","DOIUrl":"https://doi.org/10.22323/1.343.0090","url":null,"abstract":"We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to explore new physics beyond the Standard Model. Since the time and momentum of positrons from muon decay are key information in the experiment, a fast response with high granularity is demanded to silicon-strip detectors as the positron tracker. The readout ASIC is thus required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us with 5 ns time resolution. To satisfy the experimental requirements, an analog prototype ASIC was newly designed with the Silterra 180 nm CMOS technology. In the evaluation test, the time-walk was demonstrated to reach 0.8~ns with a sufficient dynamic range of 6~MIPs and pulse width of 45~ns for 1 MIP event. The design details and performance of the ASIC are discussed in this article.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flexible Printed Circuit design and testing for the High-Granularity Timing Detector for the Phase II upgrade of the ATLAS calorimeter system","authors":"M. Manzano, L. Masetti, A. Brogna","doi":"10.22323/1.343.0032","DOIUrl":"https://doi.org/10.22323/1.343.0032","url":null,"abstract":"Maria Soledad Robles Manzano∗a, Andrea Brognab, Atila Kurtb, Lucia Masettia, Paul Plattnerc, Lorenzo Polidorid , Quirin Weitzelb, on behalf of the HGTD community aInstitute of Physics and PRISMA Cluster of Excellence, Johannes Gutenberg University Mainz bDetector Laboratory, PRISMA Cluster of Excellence, Johannes Gutenberg University Mainz cInstitute of Physics, Johannes Gutenberg University Mainz dSchool of Physics and Astronomy. University of Glasgow","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128564538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PACIFIC: The readout ASIC for the SciFi Tracker of the LHCb detector","authors":"A. C. Montells, J. Cos","doi":"10.22323/1.343.0164","DOIUrl":"https://doi.org/10.22323/1.343.0164","url":null,"abstract":"","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128375249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process","authors":"S. Miryala, T. Hemperek, M. Menouni","doi":"10.22323/1.343.0029","DOIUrl":"https://doi.org/10.22323/1.343.0029","url":null,"abstract":"Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple Modular Redundancy (TMR) with clock skew insertion, a system level redundancy technique is a common practice by designers to mitigate soft errors. However, the optimal spacing between memory elements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASIC development under the framework of the CERN RD53 collaboration to characterize the soft error rates against the separation spacing and clock skew between memory elements in a TMR. This article describes the architecture and design aspects of the various test structures on the RD53SEU test chip.","PeriodicalId":400748,"journal":{"name":"Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122346878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}