一种用于时间-数字转换器的低迟滞、快速恢复的延时锁环

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018) Pub Date : 2019-05-20 DOI:10.22323/1.343.0027

B. Van Bockel, J. Prinzie, Ying Coa, P. Leroux

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引用次数: 2

摘要

本文给出了采用65纳米CMOS技术设计的1 GHz延迟锁相环(DLL)的仿真结果。该电路设计用于恶劣环境，特别是电离辐射。介绍了一种由改进的bang-bang鉴相器和三态控制器组成的新型鉴相器，单事件恢复时间小于1us。该DLL用于时间到数字转换器内部，并实现仅500fs的锁内迟滞。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis

This paper proposes the simulation results of a 1 GHz Delay Locked Loop (DLL) designed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. A novel phase detector consisting of an improved bang-bang phase detector and a 3state controller was introduced, leading to a a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter, and achieves an in lock hysteresis of only 500 fs.

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Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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