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International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.最新文献

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Performances comparison between multilevel hierarchical and mesh FPGA interconnects 多级分层和网状FPGA互连的性能比较
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1080/00207210701828069
Z. Marrakchi, H. Mrabet, Christian Masson, H. Mehrez
{"title":"Performances comparison between multilevel hierarchical and mesh FPGA interconnects","authors":"Z. Marrakchi, H. Mrabet, Christian Masson, H. Mehrez","doi":"10.1080/00207210701828069","DOIUrl":"https://doi.org/10.1080/00207210701828069","url":null,"abstract":"In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130586876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Two dimensional model for lateral photodiode 横向光电二极管的二维模型
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708671
A. Alexandra, F. Dadouche, P. Garda
{"title":"Two dimensional model for lateral photodiode","authors":"A. Alexandra, F. Dadouche, P. Garda","doi":"10.1109/DTIS.2006.1708671","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708671","url":null,"abstract":"The design of mixed signal systems on chip is nowadays challenging, especially those including active pixel sensors (APS) for imaging. To simulate such systems, it is necessary to use optoelectronic models of the behavior of the photodetectors. The most used photodetectors in CMOS technologies are vertical photodiodes, but for specific applications, lateral photodiodes are needed. Vertical photodiodes can be described by one dimensional models but in lateral photodiode, bidimensional effects appear. Therefore a physical two dimensional model of lateral photodiode has been developed. An electrical model was defined and physical parameters which take place in this model, were presented. The results were compared to an approximated one dimensional model and show that a two dimensional model is needed to simulate the light response of lateral photodiodes","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130248227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High Q-VCO with low phase noise for communications applications 高Q-VCO，低相位噪声，适用于通信应用
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708720
N. Boughanmi, D. Ben Issa, A. Kachouri, M. Samet
{"title":"High Q-VCO with low phase noise for communications applications","authors":"N. Boughanmi, D. Ben Issa, A. Kachouri, M. Samet","doi":"10.1109/DTIS.2006.1708720","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708720","url":null,"abstract":"This work describes the design and implementation of a highly integrated, low-noise VCO realized in a 0.35 mum CMOS technology. We focus on the analysis of Q-VCO whose frequence of oscillation is determined by the resonant frequency of LC tank. The Q-VCO phase noise is directly connected to the quality factor of the LC resonant circuit, which is mainly determined by the on-chip inductor in this technology. We can obtain high Q factors over 80 at 2.9 GHz. Even, Q-VCO exhibits lower phase noise performance for a given power dissipation. From a carrier at 2.9 GHz, dissipating 2.4 mA under a 2.5 V power supply and 1V tuning voltage, simulated phase noise results are -1.36 dBc/Hz at an offset of 100 kHz. And -22 dBc/Hz at an offset of 100 MHz","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low power digital design using modified GDI method 基于改进GDI方法的低功耗数字设计
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708713
P. Balasubramanian, J. John
{"title":"Low power digital design using modified GDI method","authors":"P. Balasubramanian, J. John","doi":"10.1109/DTIS.2006.1708713","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708713","url":null,"abstract":"GDI (gate diffusion input) based technique for low power combinational logic circuit design has been elaborately discussed and the advantage of this design style over static CMOS (SC) implementation and pass-transistor logic (PTL), with regard to power consumption, delay and area complexity is also described in recent literature (Morgenshtein, 2002). In this paper, we propose a couple of new GDI based cell designs, which are found to be much more power efficient in comparison with existing GDI based cell functionality. The significance of these designs is substantiated by the simulation results obtained for a 0.35 muM TSMC CMOS technology, where an improvement in power efficiency of the order of 2-3times is reported in the pre-layout stage for some widely used important digital arithmetic circuits","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
New generic GALS NoC architectures with multiple QoS 具有多重QoS的新型通用GALS NoC架构
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708722
M. Zid, A. Zitouni, A. Baganne, R. Tourki
{"title":"New generic GALS NoC architectures with multiple QoS","authors":"M. Zid, A. Zitouni, A. Baganne, R. Tourki","doi":"10.1109/DTIS.2006.1708722","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708722","url":null,"abstract":"The quality of service network on chip (QNoC) is the most effective solution that provides low latency transfers and power efficient system on chip (SoC) interconnect. This study presents two generic globally asynchronous locally synchronous (GALS) NoC architectures called GHXPolygon (for generic extended polygon) and GHXSpidergon (for generic extended spidergon). These architectures are inspired respectively from the GeNOC and Octagon NoC of TIMA laboratory, and the Spidergon called also STNoC, of STMicroelectronics. GEXSpidergon and GHXPolygon architectures are based on a central router responsible to transfers urgent messages and used in the case of clogging of the close router towards the destination. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the messages priorities. The proposed router is based on a wormhole commutation technique and the adaptive routing with an efficient path fetching algorithm based on finite state machine to avoid deadlock problems. Handshaking and aloha protocols are implemented on each router to guarantee the inter routers communication. The proposed router can be also used with other NoC architectures such as the tree and the mesh topologies The functionalities correctness have been verified by using a traffic generation VHDL based strategy","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122890362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Speeding up simulation time in EEPROM memory designs 加速EEPROM存储器设计的仿真时间
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708695
H. Aziza, B. Delsuc, J. Portal, D. Née
{"title":"Speeding up simulation time in EEPROM memory designs","authors":"H. Aziza, B. Delsuc, J. Portal, D. Née","doi":"10.1109/DTIS.2006.1708695","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708695","url":null,"abstract":"This paper presents an efficient technique to decrease simulation lime of EEPROM memory arrays. This technique is based on the complexity reduction of an existing compact EEPROM model. This original model is unsuitable when dealing with large memory arrays simulations. To overcome this limitation, the authors propose two alternative models which allow reducing time and memory space overheads when compared to the compact model. The first EEPROM model (level 1). is as simple as possible and provides fast simulation time. The second model (level 2) is a compromise between the compact model and the level 1 model. We also present simulation time results using these different models within memory arrays","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122905095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of timing jitter in inverters induced by power-supply noise 电源噪声引起的逆变器时序抖动分析
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708708
A. Strak, H. Tenhunen
{"title":"Analysis of timing jitter in inverters induced by power-supply noise","authors":"A. Strak, H. Tenhunen","doi":"10.1109/DTIS.2006.1708708","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708708","url":null,"abstract":"This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for switched-capacitor (SC) sigma-delta (SigmaDelta) analog-to-digital converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using the processes AMS 0.35mum and UMC 0.18mum. The PSN is assumed to have a white frequency distribution with independent power and ground noise. The results show that the transformation process is approximately linear and that the jitter impact decreases as transistors move deeper into the submicron domain. Furthermore, the transformation process is not symmetrical and is dependent on switching direction, even if the PMOS and NMOS sizings are such that the effects due to difference in hole and electron mobility are mitigated","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131734212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Accumulator - based compression in symmetric transparent RAM BIST 对称透明RAM BIST中基于累加器的压缩
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708661
I. Voyiatzis
{"title":"Accumulator - based compression in symmetric transparent RAM BIST","authors":"I. Voyiatzis","doi":"10.1109/DTIS.2006.1708661","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708661","url":null,"abstract":"Symmetric transparent BIST has been proposed as a means to skip the signature prediction phase during RAM testing (required in traditional transparent BIST), therefore achieving significant reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compression is performed using single input shift registers (SISRs, for bit-organized memories) or multiple input shift registers (MISRs, for word-organized memories) whose characteristic polynomials are modified during testing. In this paper the authors propose the utilization of accumulator modules for output data compression in symmetric transparent BIST for RAMs. It is shown that in this way both the hardware overhead and the complexity of the controller are considerably reduced","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Performance of adaptive filter used in CDMA system for multiple access interference suppressing CDMA系统中用于抑制多址干扰的自适应滤波器性能
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI: 10.1109/DTIS.2006.1708659
H. Marouane, A. Benabdennabi, A. Kachouri, L. Kamoun
{"title":"Performance of adaptive filter used in CDMA system for multiple access interference suppressing","authors":"H. Marouane, A. Benabdennabi, A. Kachouri, L. Kamoun","doi":"10.1109/DTIS.2006.1708659","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708659","url":null,"abstract":"In a code division multiple access (CDMA) system all users share the same frequency band and they are separated from each other by (quasi)-orthogonal spreading codes. However, on dispersive broadband channels the orthogonality among codes is disrupted and multi-user access interference (MAI) is present on the received signal. Moreover, interference among symbols and chips of the same user arises. One of the most common solutions to suppress the MAI is the use of adaptive filter. A single-user receiver based on a linear filter that minimizes the mean square error between the output and the transmitted symbols of the user of interest. This paper focuses on the performance of the adaptive filter","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing system-in-package wirelessly 无线测试系统级封装
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-09-05 DOI: 10.1109/DTIS.2006.1708683
Serge Bernard, David Andreu, M. Flottes, P. Cauvet, Herve Fleury, Fabrice Verjus
{"title":"Testing system-in-package wirelessly","authors":"Serge Bernard, David Andreu, M. Flottes, P. Cauvet, Herve Fleury, Fabrice Verjus","doi":"10.1109/DTIS.2006.1708683","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708683","url":null,"abstract":"The paper shows a new concept for testing a system-in-package (SiP) using a wireless communication. Trends of the SiP technology put more economic and technical constraints onto the test, while the contactless test techniques represent an opportunity to overcome the inherent problems. In this paper, we introduce a new test concept based on a wireless communication, a specific test access mechanism (TAM), and an optimised architecture. Although this approach is dedicated to an intermediate test of SiP, we explore other potential applications of this technology","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133920078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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