多级分层和网状FPGA互连的性能比较

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI:10.1080/00207210701828069

Z. Marrakchi, H. Mrabet, Christian Masson, H. Mehrez

{"title":"多级分层和网状FPGA互连的性能比较","authors":"Z. Marrakchi, H. Mrabet, Christian Masson, H. Mehrez","doi":"10.1080/00207210701828069","DOIUrl":null,"url":null,"abstract":"In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Performances comparison between multilevel hierarchical and mesh FPGA interconnects\",\"authors\":\"Z. Marrakchi, H. Mrabet, Christian Masson, H. Mehrez\",\"doi\":\"10.1080/00207210701828069\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed\",\"PeriodicalId\":399250,\"journal\":{\"name\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"volume\":\"49 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1080/00207210701828069\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/00207210701828069","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文研究了一种新型多级分层FPGA (MFPGA)。具体架构包括两个单向可编程网络:一个基于蝴蝶胖树拓扑的向下网络和一个特殊的向上网络。开发了新的工具来放置和路由该架构上的几个基准电路。与传统对称的曼哈顿网格结构相比，MFPGA可以实现更小的电路面积和更高的速度

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Performances comparison between multilevel hierarchical and mesh FPGA interconnects

In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed

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International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.

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