{"title":"Scalability study of In0.7Ga0.3As HEMTs for 22nm node and beyond logic applications","authors":"E. Hwang, S. Mookerjea, M. Hudait, S. Datta","doi":"10.1109/DRC.2010.5551941","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551941","url":null,"abstract":"Compound semiconductor high electron mobility transistors (HEMTs) have recently gained a lot of interest for future high-speed, low-power logic applications due to their high mobility and high effective carrier velocity [1]. Conventional In<inf>0.7</inf>Ga<inf>0.3</inf>As HEMTs with 50 to 150nm gate-length (L<inf>G</inf>) have been experimentally demonstrated [2] with excellent device performance. In this paper, (i) we use two-dimensional numerical drift-diffusion simulations [3] to model the conventional In<inf>0.7</inf>Ga<inf>0.3</inf>As HEMTs with different L<inf>G</inf> from 15 to 200nm and investigate its scalability for future logic applications. (ii) An accurate estimation of effective mobility (μ<inf>eff</inf>) and effective carrier velocity (injection) is presented, highlighting the relevance of ballistic mobility in these short-channel HEMTs. (iii) Due to degradation in performance of the conventional scaled In<inf>0.7</inf>Ga<inf>0.3</inf>As HEMT at L<inf>G</inf>=15nm, three novel HEMT device architectures are studied and the design for the ultimate scaled transistor is proposed.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"591 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Saripalli, D. Mohata, S. Mookerjea, S. Datta, V. Narayanan
{"title":"Low Power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs","authors":"V. Saripalli, D. Mohata, S. Mookerjea, S. Datta, V. Narayanan","doi":"10.1109/DRC.2010.5551859","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551859","url":null,"abstract":"We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell [1] has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors to maintain state. In this paper, we introduce a p-type TFET with a degenerately doped source, which has a kT/q sub-threshold slope, compared to an n-type TFET which has a sub-kT/q slope. This difference in sub-threshold behaviour of the DDS PTFET and DDS NTFET helps to maintain the IOFF ratio which is required for cell stability. We explain the temperature dependent sub-threshold characteristics of the In0.53Ga0.47As (DDS) p-TFET by analyzing the position of the Fermi level in the source of the p-TFET as a function of source doping. Further, the asymmetric source drain architecture of the TFETs is exploited to solve the adjacent bit flip problem of unselected Loadless 4T SRAM cells during a column write operation. Finally, we include a comparison of the leakage energy and cell access time of the TFET based SRAM cell and benchmark its performance relative to state-of-the-art CMOS based 6T SRAM cells.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shahrukh A. Khan, P. Kuo, A. Jamshidi-Roudbari, M. Hatalis
{"title":"Effect of uniaxial tensile strain on electrical performance of amorphous IGZO TFTs and circuits on flexible Metal foils","authors":"Shahrukh A. Khan, P. Kuo, A. Jamshidi-Roudbari, M. Hatalis","doi":"10.1109/DRC.2010.5551869","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551869","url":null,"abstract":"Inexpensive and light-weight flexible displays and sensor electronics would be more rugged and portable than the more conventional rigid substrate-based electronics. Till date, large area flexible systems are enabled by a-Si:H or organics which suffer from low mobilities that limit their use in driver electronics that require higher current drive. This is where oxide-semiconductor (amorphous Indium Gallium Zinc Oxide, IGZO in particular) based thin-film transistors (TFTs) provide an attractive alternative to silicon-based TFTs. Therefore, one needs to study the interdependence of mechanical flexing and electrical performance of these devices as they find applications in flexible large area based electronics. This study systematically investigates the influence of tensile strain on IGZO TFTs and ring oscillators fabricated on flexible stainless steel substrates.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"62 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116436829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Ante, F. Letzkus, J. Butschke, U. Zschieschang, J. Burghartz, Klaus Kern, H. Klauk
{"title":"Top-contact organic transistors and complementary circuits fabricated using high-resolution silicon stencil masks","authors":"F. Ante, F. Letzkus, J. Butschke, U. Zschieschang, J. Burghartz, Klaus Kern, H. Klauk","doi":"10.1109/DRC.2010.5551894","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551894","url":null,"abstract":"The maximum operating frequency of a field-effect transistor is inversely proportional to its lateral dimensions. Organic thin-film transistors (TFTs) with dimensions of ∼1 µm or less have been fabricated by photolithography [1], electron-beam lithography (EBL) [2], nano-imprint lithography (NIL) [3], sub-femtoliter inkjet printing (SIJ) [4] and self-aligned inkjet printing (SAP) [5]. Some of these methods (EBL, SIJ, SAP) have small throughput, others (EBL, NIL, photolithography) involve solvents or high process temperatures. Since high-mobility small-molecule organic semiconductors often undergo phase transitions when exposed to solvents or heat [6,7], these methods are in general not suitable to pattern source and drain contacts on top of such semiconductors. As an alternative, high-resolution stencil masks offer the possibility to pattern top contacts with high throughput and without the need for solvents or elevated temperatures. For example, Jin et al. reported top-contact pentacene TFTs with a channel length of 1.8 µm fabricated by using a global silicon back gate and a high-resolution silicon nitride stencil mask [8]. For devices with short channel lengths, top-contact organic TFTs usually provide better performance than bottom-contact TFTs [9].","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124035378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel multi-bit non-uniform channel charge trapping memory with virtual-source NAND array","authors":"H. Gu, L. Pan, P. Zhu, D. Wu, Z. Zhang, J. Xu","doi":"10.1109/DRC.2010.5551966","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551966","url":null,"abstract":"Abstract Withdrawn","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122617903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structure and doping effects in carbon heterojunction FETs towards barrier-free inter-band tunneling","authors":"Y. Yoon, S. Salahuddin","doi":"10.1109/DRC.2010.5551923","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551923","url":null,"abstract":"We have shown that it may be possible to use a CNT-GNR heterostructure to obtain a novel transistor action such that (i) at low voltage the device acts like a tunneling transistor, reducing the voltage requirement below the classical limit and (ii) at high voltages the tunnel barrier is effectively diminished, thus allowing a large drive current. Therefore, such a heterostructure may combine the best practices of both a tunneling FET and a conventional MOSFET in the same device structure and thus guide a way in designing ultra low-power carbon-based electronics.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116764641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transistors: Past, present, future, and future-er","authors":"S. Natarajan","doi":"10.1109/DRC.2010.5551861","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551861","url":null,"abstract":"In this talk, we will explore the history, current status, and future prospects for the transistor. We review the 30+ year past, focusing primarily on the work-horse planar CMOSFET, as well as the incredible state of integrated electronics it has enabled. We look at the more recent past, where the “end of scaling” and death of the planar MOSFET has been repeatedly forecast, and discuss critical innovations on strained-silicon and high-k/metal-gate transistors which have extended MOSFET scaling. Next we look to the near future, to strong candidates for the generations of process technology to come and challenges which must be overcome to enable them. Finally, we peer into our crystal ball in the distant future and consider the viable options for the next switching element to continue the march of integrated electronics.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Varga, S. Liu, M. Niemier, W. Porod, X.S. Hu, G. Bernstein, A. Orlov
{"title":"Experimental demonstration of fanout for Nanomagnet Logic","authors":"E. Varga, S. Liu, M. Niemier, W. Porod, X.S. Hu, G. Bernstein, A. Orlov","doi":"10.1109/DRC.2010.5551852","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551852","url":null,"abstract":"Nanoscale magnets can process and move information via fringing field interactions. Wires, gates, and inverters have been demonstrated (Fig. 1a-c)1 - all at room temperature. Nanomagnet Logic (NML) devices can be made with standard lithographic techniques, and even with drive circuitry overhead, energy/performance gains over CMOS are possible2. Still, demonstrating wires and gates in isolation does not equate to a deployable digital system. For systems, it is widely accepted that a technology must meet five criteria3 - (i) a device should have non- linear response characteristics, (ii) the output of one device must drive another, (iii) unwanted dataflow (or feedback) should not occur, (iv) a device must enable a functionally complete logic set, and (v) power amplification (or gain greater than 1) is needed. We report experimental demonstration of the fifth tenet of digital logic - fanout.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115116919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Depletion-mode pseudomorphic In0.22Ga0.78As-channel MOSFETs with InAlP native oxide gate dielectric for RF applications","authors":"X. Xing, W. Yuan, D. Hall, P. Fay","doi":"10.1109/DRC.2010.5551889","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551889","url":null,"abstract":"Pseudomorphic high electron-mobility transistors (pHEMTs) have demonstrated excellent high-speed, power and noise performance, and have been widely used in microwave and millimeter-wave circuits, as well as wireless and optoelectronic applications [1]. Replacing the Schottky gate contacts in pHEMTs with insulating metal-oxide-semiconductor structures (pMOSFETs) can result in increased allowable gate voltage swing, while at the same time suppressing gate current due to the higher effective gate potential barrier. Here we present the first pseudomorpic In0.22Ga0.78As-channel MOSFETs with InAlP native oxide gate dielectric operating in depletion mode with significant performance enhancement compared to prior GaAs-channel MOSFETs with same gate dielectric [2], indicating clear promise of such devices for future RF applications.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115128376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yanning Sun, George Tuleski, Shu-Jen Han, W. Haensch, Zhihong Chen
{"title":"Improve variability in carbon nanotube FETs by scaling","authors":"Yanning Sun, George Tuleski, Shu-Jen Han, W. Haensch, Zhihong Chen","doi":"10.1109/DRC.2010.5551959","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551959","url":null,"abstract":"Carbon nanotube transistors are shown to have large performance variation due to their diameter variation, which is not acceptable to VLSI technology. We demonstrate that by proper scaling we can reach >2 mA/µm on-state current in 90% of our nanotube devices. More importantly, we demonstrate proper scaling can reduce the current variation by 2 orders of magnitude and mitigate the impact of tube diameter distribution.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}