68th Device Research Conference最新文献

{"title":"Investigation of the scalability of ultra thin body (UTB) double gate tunnel FET using physics based 2D analytical model","authors":"Lu Liu, S. Datta","doi":"10.1109/DRC.2010.5551890","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551890","url":null,"abstract":"Tunnel Field Effect Transistor (TFET) is an emerging ultra-low power transistor that can, in principle, exhibit <60mV/dec slope. While a limited number of 1-dimensional analytical modeling work [1][2] have been reported till date, the influence of drain bias on the transistor characteristics is not included in these models. In this work, we present a 2-dimensional analytical model of double gate ultra thin body TFET (Fig. 1) taking into consideration the influence of the drain bias. Based on this model, we show that the Tunnel FETs exhibit superior short channel effects than their MOSFET counterparts at comparable dimensions, but the scalability of the former degrades at a faster rate with gate length scaling.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graphene based heterostructure tunnel-FETs for low-voltage/high-performance ICs","authors":"Yasin Khatami, M. Krall, Hong Li, Chuan Xu, K. Banerjee","doi":"10.1109/DRC.2010.5551939","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551939","url":null,"abstract":"The characteristics of the wide-narrow GNR T-FET were studied. The proposed device utilizes the small bandgap of wide-GNR to achieve high I<inf>ON</inf> and the high bandgap of narrow-GNR to attain low I<inf>OFF</inf>. The design space for the bandgap/width of the two regions was studied. The design parameters can be optimized to achieve I<inf>ON</inf> as high as 1.3 mA/µm, I<inf>ON</inf>/I<inf>OFF</inf> ratio as high as 10⁹, and S as small as 10 mV/dec at V<inf>DD</inf>=0.5 V. Compared to the HP MOSFET with L<inf>g</inf>=25 nm [6], the wide-narrow GNR T-FET exhibits 2X and 10⁴X improvement in I<inf>ON</inf> and I<inf>ON</inf>/I<inf>OFF</inf> ratio at V<inf>DD</inf>=0.5 V, which makes it suitable for HP/LP applications.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127569864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Kinetic Monte Carlo simulation of resistive switching and filament growth in electrochemical RRAMs","authors":"Feng Pan, V. Subramanian","doi":"10.1109/DRC.2010.5551973","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551973","url":null,"abstract":"In recent years, Resistive Random Access Memory (RRAM) has received attention as a promising candidate for scaled memories [1]. An atomic-scale simulation tool that can describe the dynamics of RRAM operation is still lacking. Using a two dimensional (2D) Kinetic Monte Carlo (KMC) method, we have simulated the switching I–V characteristic and related filament morphology of electrochemical metallic (ECM) type RRAMs. These are considered promising for both memory and configurable logic applications due to their low-power switching and very low resistance on-state. As a result, an understanding of the underlying physics and dependencies is particularly important. In our simulation, because most important physical and chemical processes, such as oxidation, reduction, metal crystallization, ion adsorption, desorption and transportation have been taken into account, the simulated I–V curve accurately shows all the typical RRAM SET stage behaviors, including the filament overgrowth effect.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124068621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly scalable vertical bandgap-engineered NAND flash memory","authors":"Seongjae Cho, Yoon Kim, W. Shim, D. Li, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/DRC.2010.5551967","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551967","url":null,"abstract":"In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put together to have a common vertical channel as shown in Fig. 1(a). The biggest merit in this array feature is that half-level reduction in footprint can be achieved by using the sidewall control gates as shown in Fig. 1(b). Due to the vertical channel, the channel length can be simply controlled by anisotropic dry etch, which suppresses short channel effects (SCEs) effectively and enlarges the sensing margin. Fig. 1(c) shows the schematic view of the array with circuit symbols. Also, in this novel flash memory, the memory storage node uses a bandgap-engineered (BE) multi-layer, where the oxide-nitride-oxide triple-layer replaces the tunnel oxide to improve the performances in operations [1–3]. The process architecture for fabricating the vertical BE-NAND flash memory is summarized in Fig. 2. The fin structures in both bitline (BL) and wordline (WL) directions have been formed by sidewall spacer patterning [4]. Among the several possible combinations of materials [5–6], nitride (Si3N4) and TEOS are used for the sidewall spacer and the supporting dummy pattern, respectively. Fig. 3 and 4 shows the process flow for Si fin constructions in both directions. After the fin consisted of Si-STI alternating pillars is formed in the WL direction, ONONO (20/20/20/60/60 Å) multi-layer is deposited. All the oxide layers were deposited by medium temperature oxidation (MTO) in an ambient of N2 160 sccm and DCS 40 sccm. The tunneling and storage nitride layers were deposited by LPCVD in the ambient of NH3 30 sccm/DCS 10 sccm/750 °C and NH3 100 sccm/DCS 30 sccm/785 °C, respectively. Subsequently, physically separated sidewall control gates used as WLs are formed by etch-back process. Fig. 5(a) through (c) show the images for fin structures and top view of the vertical BE-NAND flash with independent sidewall gates. After ILD/CMP/metallization/alloy, the fabrication is completed.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131005716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of InP barrier layer thicknesses and different ALD oxides on device performance of In0.7Ga0.3As MOSFETs","authors":"Han Zhao, Ning Kong, Yen‐Ting Chen, Yanzhen Wang, F. Xue, F. Zhou, S. Banerjee, Jack C. Lee","doi":"10.1109/DRC.2010.5551942","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551942","url":null,"abstract":"III–V materials are attractive for achieving enhanced device performance due to their high electron mobility. It has been reported that buried channel InGaAs MOSFETs with barrier layers¹⁻³ can achieve much higher electron mobility than surface channel InGaAs MOSFETs⁴⁻⁵ and several orders lower gate leakage current than HEMTs⁶. However, the effects of barrier layer thicknesses and oxide/barrier interface quality on device performance have not been studied. In this paper, InP barrier was used instead of InAlAs barrier due to its better interface quality with gate oxides⁷. The effects of different InP barrier thicknesses on device performance were investigated. We have also deposited different ALD gate oxides (single Al<inf>2</inf>O<inf>3</inf>, HfO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> bilayer) and studied the influence of various oxides on oxide/barrier interface and device characteristics. Equivalent oxide thicknesses (EOT) of In<inf>0.7</inf>Ga<inf>0.3</inf>As MOSFETs with InP barrier have been scaled to 1.2 nm using HfO<inf>2</inf>. Record high effective channel mobility μ<inf>eff</inf> of 4584 cm²/Vs and small subthreshold swing of 96 mV/dec have been achieved using 5 nm InP barrier and 4 nm Al<inf>2</inf>O<inf>3</inf> oxide. Ring-type In<inf>0.7</inf>Ga<inf>0.3</inf>As MOSFETs were fabricated on MBE 10nm undoped In<inf>0.7</inf>Ga<inf>0.3</inf>As channel with two different InP barrier thicknesses (3 nm & 5 nm) (fig.1). The n⁺ InGaAs contact layer was selectively removed at channel region. Various gate oxides (4 – 8 nm Al<inf>2</inf>O<inf>3</inf>, 5 nm HfO<inf>2</inf> and 1 nm Al<inf>2</inf>O<inf>3</inf>/4 nm HfO<inf>2</inf> bilayer) were deposited by ALD. After that, TaN was deposited for gate electrode and AuGe/Ni/Au for source and drain ohmic contact.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132585982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced spin injection into single layer graphene with atomically smooth MgO barrier","authors":"W. Han, K. Pi, K. McCreary, Yan Li, R. Kawakami","doi":"10.1109/DRC.2010.5551950","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551950","url":null,"abstract":"Single layer graphene (SLG) is a promising material for spintronics due to predictions of long spin life time, and unusual spin dependent behaviors such as half-metallic ferromagnetism for graphene nanoribbons. Previously, we fabricated SLG spin valves utilizing transparent contacts Co/SLG with MgO masking layer, and observed gate tunable spin transport at room temperature (RT) [1]. For the non-local MR measurement (Figure 1a), spin is injected at electrode E2 and detected at E3. Figure 1b shows the non-local MR loop for a SLG spin valve with transparent contacts as the magnetic field is swept up (black curve) and swept down (red curve).","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133619717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microelectronics in the “More than Moore” era","authors":"K. Wise","doi":"10.1109/DRC.2010.5551936","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551936","url":null,"abstract":"In the fifty years since integrated circuits made their debut, we have witnessed amazing progress in the ability to perform electronic functions. Progress in microprocessors, memory, and data conversion has revolutionized data processing, control, communications, and the way we live. The number of transistors/ chip has increased by a factor of a billion and performance has improved at least a million-fold, with corresponding decreases in cost. For forty years, this progress has been driven by scaling and “Moore's Law”; however, fabrication facility cost has now increased to the point where it now exceeds the GNP of many countries, forcing many companies to go fabless. It also appears that the scaling paradigm is coming to an end, at least using devices as we know them. As a result, intense efforts on chip-stacking, through-silicon vias (TSVs), and new materials such as graphene are underway [1].","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"T-gate technology for N-polar GaN-based self-aligned MIS-HEMTs with state-of-the-art fMAX of 127 GHz: Pathway towards scaling to 30nm GaN HEMTs","authors":"Nidhi, S. Dasgupta, David F. Brown, S. Keller, J. Speck, U. Mishra","doi":"10.1109/DRC.2010.5551884","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551884","url":null,"abstract":"N-polar GaN/AlGaN HEMTs have been of interest to the nitride community recently due to their several advantages over Ga-polar GaN-based HEMTs such as lower contact resistance [1], better electron confinement [2], and enhancement mode operation. For very high frequency performance, it is necessary to scale the parasitic elements in the device along with the gate length. First reports on scaled self-aligned HEMTs on N-face with regrown access regions [3] demonstrated minimization of access resistances which resulted in linear scaling of total delay up to 120 nm gate length (Fig. 1). However, even though excellent fT.Lg products of 16.8 GHz-µm were achieved, very low fMAX of 17 GHz was achieved due to high resistivity of the W-gates in the gate-first process.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116395666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electric field control of spin precession in a spin-injected Field Effect Transistor","authors":"M. Johnson, H. Koo, J. Eom, S.H. Han, J. Chang","doi":"10.1109/DRC.2010.5551952","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551952","url":null,"abstract":"Two decades ago, Datta and Das [1] predicted that the source-drain conductance of a spin-injected Field Effect Transistor (spin FET) would oscillate periodically with monotonically increasing gate voltage as a consequence of the Rashba spin-orbit interaction in the channel. The effect relies on ballistic transport and a relativistic transformation, and is unique because an electric field modulates the orientation of a magnetic moment. We have observed Datta-Das oscillations in a spin FET at cryogenic temperatures [2].","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115071560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-hysteretic ferroelectric tunnel FET with improved conductance at Curie temperature","authors":"L. Lattanzio, G. Salvatore, A. Ionescu","doi":"10.1109/DRC.2010.5551937","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551937","url":null,"abstract":"Tunnel FETs (TFETs) have attracted much interest in the last decade for their potential to be used as small slope switches [1,2], suitable for future logic circuits operating with a supply voltage smaller than 0.5 V and for reduced Ioff levels. It has been shown that these devices highly benefit from a high gate dielectric constant, as the gate-channel capacitive coupling is improved, positively impacting the band-to-band tunneling at low voltages [3]. Temperature-dependent performances have also been studied: models and experiments show a slight degradation of TFET subthreshold slope and an increase in the Ion with temperature, due to energy bandgap narrowing [4,5]. In parallel, the integration of ferroelectric materials in MOSFET gate stacks is being considered for enhancing their subthreshold swing [6]. Furthermore, ferroelectric materials show a unique temperature behavior. According to Landau's theory, at the Curie temperature (TC) the relative dielectric permittivity εFe ideally diverges [7] (Fig. 1).","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121387578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}