Effects of InP barrier layer thicknesses and different ALD oxides on device performance of In0.7Ga0.3As MOSFETs

Abstract

III–V materials are attractive for achieving enhanced device performance due to their high electron mobility. It has been reported that buried channel InGaAs MOSFETs with barrier layers¹⁻³ can achieve much higher electron mobility than surface channel InGaAs MOSFETs⁴⁻⁵ and several orders lower gate leakage current than HEMTs⁶. However, the effects of barrier layer thicknesses and oxide/barrier interface quality on device performance have not been studied. In this paper, InP barrier was used instead of InAlAs barrier due to its better interface quality with gate oxides⁷. The effects of different InP barrier thicknesses on device performance were investigated. We have also deposited different ALD gate oxides (single Al2O3, HfO2 and Al2O3/HfO2 bilayer) and studied the influence of various oxides on oxide/barrier interface and device characteristics. Equivalent oxide thicknesses (EOT) of In0.7Ga0.3As MOSFETs with InP barrier have been scaled to 1.2 nm using HfO2. Record high effective channel mobility μeff of 4584 cm²/Vs and small subthreshold swing of 96 mV/dec have been achieved using 5 nm InP barrier and 4 nm Al2O3 oxide. Ring-type In0.7Ga0.3As MOSFETs were fabricated on MBE 10nm undoped In0.7Ga0.3As channel with two different InP barrier thicknesses (3 nm & 5 nm) (fig.1). The n⁺ InGaAs contact layer was selectively removed at channel region. Various gate oxides (4 – 8 nm Al2O3, 5 nm HfO2 and 1 nm Al2O3/4 nm HfO2 bilayer) were deposited by ALD. After that, TaN was deposited for gate electrode and AuGe/Ni/Au for source and drain ohmic contact.