R. Gomez, E. R. Burke, R. Madabhushi, I. Mayergoyz
{"title":"Erasure processes of magnetic memories at the microscopic level","authors":"R. Gomez, E. R. Burke, R. Madabhushi, I. Mayergoyz","doi":"10.1109/NVMT.1996.534670","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534670","url":null,"abstract":"The microscopic erasure characteristics of the most common types of magnetic storage media have been investigated using magnetic force microscopy. The micromagnetic evolution of recorded patterns on thin film rigid disk and flexible media have been observed as a function of an applied external field, and the reduction of magneto-optic media marks has been investigated as a function of heating temperature. Specific stages of the erasure process exhibit unique characteristics for each medium. The initial erasure stages for both types of ferromagnetic media show similar behaviour and are characterized by the expansion of the favoured domains. The middle and final stage behaviours are markedly different. For the thin film case, magnetization reversal occurs by nucleation and growth while for the particulate media, reversal occurs primarily through localized cluster switching. These results were correlated with their macroscopic magnetization curves and their diverging characteristics can be attributed to their differing interparticle coupling interaction. The initial stage of erasure of magneto-optic media is accompanied by the anisotropic displacement of the domain walls which introduces shape irregularities of the original circular marks. With increase in temperature, the microdomains that comprise the individual marks become apparent as each microdomain independently diminish in size. Pinning at the mechanical grooves has been found to be mainly responsible for retarding domain collapse.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design issues for use of flash memory devices in solid state recorders","authors":"B. Kaufman","doi":"10.1109/NVMT.1996.534688","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534688","url":null,"abstract":"Summary form only given. Solid State Recorders (SSR) form a rapidly growing class of memory systems. Applications range from small (Tb) units capturing airborne reconnaissance data with rates approaching 1 Gb/s. A near universal requirement for SSRs is to be capable of nonvolatile data storage, with retentivity ranging from hours upward. Flash memory technology offers an attractive approach to designing SSRs. While inherently nonvolatile, having high (32 Mb and growing) bit density and wide availability as COTS parts, flash has two major limitations: endurance and slow write speed. These two attributes are barriers to meeting requirements of high performance SSRs. This paper reviews characteristics of flash technology as applied to SSR applications, discusses trade-offs and design techniques for overcoming their limitations and offers some examples of SSR performance presently attainable with COTS flash devices.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115755356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Guillaumot, H. Achard, P. Candelier, S. Deleonibus, F. Martin
{"title":"Flash EEPROM cells using shallow trench isolation","authors":"B. Guillaumot, H. Achard, P. Candelier, S. Deleonibus, F. Martin","doi":"10.1109/NVMT.1996.534673","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534673","url":null,"abstract":"The recent flash EEPROM market growth of very large products has pointed out the necessity for very aggressive design rule, especially for isolation whose pitch needs to be shrunk; additionaly, residual topography must be reduced and gate oxide quality must comply with flash program and erase mechanisms. However, internal supply voltage has to remain in the same range of 15 to 17 volts. To meet these requirements, LArge Tilted Implanted Shallow Trench Isolation (LATI STI) and Chemical Mechanical Planarization (CMP) are used. This paper presents a CMP LATI STI process which demonstrates a good isolation and gate oxide quality, a way to control side wall parasitic transistor and narrow channel effect; and finally flash EEPROM cells with equivalent or better characteristics than the ones processed with standard PBL isolation.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125899923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Zurcher, R.E. Jones, P. Chu, D. Taylor, B. White, S. Zafar, B. Jiang, Y. Lii, S. J. Gillespie
{"title":"Ferroelectric nonvolatile memory technology: applications and integration challenges","authors":"P. Zurcher, R.E. Jones, P. Chu, D. Taylor, B. White, S. Zafar, B. Jiang, Y. Lii, S. J. Gillespie","doi":"10.1109/NVMT.1996.534687","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534687","url":null,"abstract":"Summary form only given. We discuss different integration approaches, their challenges, and problems specific to the integration of ferroelectric materials into Si-CMOS. The focus is on our ongoing integration efforts using a 1 K test vehicle with 2T/2C memory architectures in single level poly and single level metal with a 0.8 /spl mu/m front-end and a 1.2 /spl mu/m back-end. The ferroelectric capacitor module comprises Pt electrodes and a layered perovskite SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) dielectric. The capacitor module is integrated between the CMOS front-end and the metal back-end. This approach dictates processing temperatures below 900/spl deg/C during the ferroelectric module processing and below 450/spl deg/C after the metal deposition. Oxide ceramics like SET or PZT are easily damaged in plasma processes. Examples of such process damage and recovery by oxygen anneals are discussed. Progress in patterning capacitor materials is described. Finally, the post-metal anneal dilemma of not being able to perform hydrogen (i.e. forming gas) anneals for transistor recovery is discussed. Ferroelectric capacitor properties and transistor characteristics after integration are shown.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A vision of ultra-high density memory","authors":"C. Morehouse","doi":"10.1109/NVMT.1996.534665","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534665","url":null,"abstract":"Skeptics have been questioning the extensibility of conventional magnetic storage technologies for many years, and have been proved wrong when they predict the end of the line for a particular storage scheme (flexible disks and tapes come to mind). Disk drives will certainly continue to improve and overcome the difficult barriers being faced in the march to 10 Gbit/in2 and beyond. However, it is worthwhile to ask if there might be an alternative technology which could jump ahead of the disk drive areal density growth line. In order to challenge the well-established disk industry, the new technology must have a significant density advantage, as well as maintaining cost and performance parity. The author shows the rigid disk areal density growth, along with a fanciful growth curve positioned roughly two orders of magnitude above the disk curve. The ultra-high density of this storage vision leads us to label the concept Atomic Resolution Storage. The system could use arrays of magnetic columns.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Holographic 3D disks","authors":"D. Psaltis, A. Pu","doi":"10.1109/NVMT.1996.534666","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534666","url":null,"abstract":"The performance characteristics of an experimental holographic 3D disk system are described. A surface density of 10 bits//spl mu/m/sup 2/ is experimentally demonstrated using a 100 /spl mu/m thick photopolymer as the recording medium.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132978847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nonvolatile memory requirements in a mobile computing environment","authors":"B. Bickford","doi":"10.1109/NVMT.1996.534660","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534660","url":null,"abstract":"In order to discuss the nonvolatile memory requirements of mobile systems it is first necessary to define what is meant by \"mobile computing environment\". This paper begins by distinguishing what is meant by a mobile computing environment and how this environment dictates certain design goals. It is these design goals that are driving two distinct classes of mobile computing products: handheld devices (PDAs, calculators) and mobile computers (notebooks, subnotebooks). These classes are defined in terms of the end-user model on which they are based. It is this end-user model that dictates the architectural requirements of the class. The architecture of the class certainly places demands on the system which in part are being met with nonvolatile memory. The demands that are currently being met with nonvolatile memory are explored for both of the classes of mobile systems. The paper then discusses the current state of the mobile computing environment and how the evolution of this environment will result in the erosion of the architectural differences between the two classes. As the two architectures become less delineated there will be other opportunities for nonvolatile memory. These other opportunities are explored and the role that nonvolatile memory will serve in future mobile systems is discussed.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Projected applications, status and plans for Honeywell high density, high performance, nonvolatile memory","authors":"G. B. Granley, A. Hurst","doi":"10.1109/NVMT.1996.534686","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534686","url":null,"abstract":"The foundation and basis for the Honeywell nonvolatile memory program is the proven, radiation hard, CMOS technology, combined with the proven, radiation hard, MRAM nonvolatile memory technology. These demonstrated capabilities allow the Honeywell team to focus on the most critical elements, the production release of the current AMR nonvolatile products and the development of scalable GMR storage elements capable of supporting 4 Gbit/cm/sup 2/ nonvolatile memory technology.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"3 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Overview of the DARPA non-volatile magnetic memory program","authors":"F. Patten, S.A. Wolf","doi":"10.1109/NVMT.1996.534659","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534659","url":null,"abstract":"This paper will describe a very new program at DARPA that has as one of its major goals the development of nonvolatile magnetic random access memory that has the potential to be radiation hard, very dense (comparable to DRAM) and very fast (comparable to SRAM). This memory will utilize spin polarized transport through multilayers, either taking advantage of the Giant Magneto-Resistive Effect (GMR), the Spin Valve Effect (SV) or Spin Tunneling (ST).","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128581213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flash memory mass storage technology tradeoffs","authors":"J. F. Forella","doi":"10.1109/NVMT.1996.534682","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534682","url":null,"abstract":"A large capacity mass storage system using solid state flash memory as the memory element is an advantage in severe environments. The relatively high density of the current flash memory devices supports the development of a large capacity mass storage system using this technology, however, the advantage of an entirely solid state system in severe environments brings some disadvantages. These disadvantages, relating to reliability, write thruput and cost can be minimized with the use of built-in spare capacity, array architecture, redundancy and modular components.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115897270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}