Flash EEPROM cells using shallow trench isolation

Abstract

The recent flash EEPROM market growth of very large products has pointed out the necessity for very aggressive design rule, especially for isolation whose pitch needs to be shrunk; additionaly, residual topography must be reduced and gate oxide quality must comply with flash program and erase mechanisms. However, internal supply voltage has to remain in the same range of 15 to 17 volts. To meet these requirements, LArge Tilted Implanted Shallow Trench Isolation (LATI STI) and Chemical Mechanical Planarization (CMP) are used. This paper presents a CMP LATI STI process which demonstrates a good isolation and gate oxide quality, a way to control side wall parasitic transistor and narrow channel effect; and finally flash EEPROM cells with equivalent or better characteristics than the ones processed with standard PBL isolation.