发布求助
文献互助 智能选刊 最新文献

Proceedings of Nonvolatile Memory Technology Conference最新文献

筛选
英文 中文
2.7 volt-only NOR-based flash memory meets portable system requirements 2.7伏纯nor闪存满足便携式系统要求
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534672
P.C. Henry
{"title":"2.7 volt-only NOR-based flash memory meets portable system requirements","authors":"P.C. Henry","doi":"10.1109/NVMT.1996.534672","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534672","url":null,"abstract":"NOR-based flash devices represent 95 percent of the flash memory sold in 1995. The NOR-based flash memory devices are widely used in application to store control code. The first 5.0 V-only flash memory devices, introduced in 1991, which combined Embedded Algorithms, single power-supply operation, and 100,000 program/erase cycle endurance, has become the industry standard. However, there is an emerging need for 2.7 V flash memory products to service the need of battery-powered systems. This paper discusses the general flash memory market, 2.7 V flash alternatives, 2.7 V flash applications, and design considerations for a 2.7 V system.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130181750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A dual gate flash EEPROM cell with two-bits storage capacity 具有两位存储容量的双门EEPROM单元
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534676
M. Lorenzini, M. Rudan, G. Baccarani
{"title":"A dual gate flash EEPROM cell with two-bits storage capacity","authors":"M. Lorenzini, M. Rudan, G. Baccarani","doi":"10.1109/NVMT.1996.534676","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534676","url":null,"abstract":"In this paper, a dual-gate flash EEPROM cell is proposed which allows the storage of two bits at the expense of a slight increase in cell size. Extensive simulations show that the basic functions of the flash cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. A simplified model based on the equivalent circuit of the cell allows a qualitative interpretation of the obtained results, and is of great help for the optimization of the cell parameters.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132444529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Trends and challenges 趋势与挑战
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534661
R. Fedorak
{"title":"Trends and challenges","authors":"R. Fedorak","doi":"10.1109/NVMT.1996.534661","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534661","url":null,"abstract":"Conditions that influence the semiconductor nonvolatile memory (NVM) technology advances and development are under very limited control by the technologist and device or system innovators. Factors such as national technical policy, national technology initiatives, global competition, the general economic conditions, and the particular conditions of a target market will shape the opportunities for success or failure of particular memory development approach. Technologist and system planners should seek to understand these forces if they wish to participate in the processes that will set their agenda.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114525636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 205
A low voltage SONOS nonvolatile semiconductor memory technology 一种低电压SONOS非易失性半导体存储技术
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534669
Marvin H. White, Yang Yang, A. Purwar, M. French
{"title":"A low voltage SONOS nonvolatile semiconductor memory technology","authors":"Marvin H. White, Yang Yang, A. Purwar, M. French","doi":"10.1109/NVMT.1996.534669","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534669","url":null,"abstract":"The triple dielectric SONOS (polysilicon-blocking oxide-silicon nitridetunnel oxide-silicon) structure is an attractive candidate for high density E/sup 2/PROM's suitable for semiconductor disks and a replacement for high-density DRAMS. Low programming voltages (5 V) and high endurance (greater than 10/sup 7/ cycles) are possible in this multi-dielectric technology as the intermediate Si/sub 3/N/sub 4/ layer is scaled to thicknesses of 50 A. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and as associated CMOS peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F/sup 2/, where F is the technology feature size. A 0.20 /spl mu/m feature size permits a 1TC area of 0.24 /spl mu/m/sup 2/ for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 123
Multi-level charge storage in source-side injection flash EEPROM 源侧注入闪存EEPROM的多级电荷存储
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534675
D. Montanari, J. van Houdt, D. Wellekens, G. Vanhorebeek, L. Haspeslagh, L. Deferm, G. Groeseneken, H. Maes
{"title":"Multi-level charge storage in source-side injection flash EEPROM","authors":"D. Montanari, J. van Houdt, D. Wellekens, G. Vanhorebeek, L. Haspeslagh, L. Deferm, G. Groeseneken, H. Maes","doi":"10.1109/NVMT.1996.534675","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534675","url":null,"abstract":"The growing demand for high-density flash memories in portable computing, smart cards and telecommunications applications has boosted the efforts on flash memory cell size scaling and cost reduction. In order to further increase the storage capability and, consequently, reduce the cost per bit of flash memories, Multi-Level Charge Storage (MLCS) techniques have recently gained a lot of interest. Furthermore, MLCS is considered a viable route for increasing embedded flash density as well. The devices investigated so far rely either on conventional Channel Hot Electron (CHE) injection or on Fowler-Nordheim tunneling (FNT) for programming. For the first time, this paper shows that Source Side Injection (SSI) is also an excellent candidate for MLCS. The main advantages of SSI for MLCS are the very narrow threshold-voltage distributions after SSI programming, the symmetrical threshold-voltage window and the overerase immunity, which allows an overall wider threshold-voltage window, and hence more separated distributions.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130597673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Self-localization of degradation process in pre-breakdown stage of thin SiO/sub 2/ films: new model and experimental procedure SiO/ sub2 /薄膜预击穿阶段降解过程的自定位:新模型和实验方法
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534680
A. Kotov
{"title":"Self-localization of degradation process in pre-breakdown stage of thin SiO/sub 2/ films: new model and experimental procedure","authors":"A. Kotov","doi":"10.1109/NVMT.1996.534680","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534680","url":null,"abstract":"We further consider the model for the degradation chain of thin SiO/sub 2/ films, which includes four stages: 1) generation of deep traps/negative space charge /spl rArr/; 2) self-localization of injection current /spl rArr/; 3) formation of local defect spot /spl rArr/; 4) appearance of leakage channel and its development into the breakdown region. A generation of space charge during stages 1 and 2 leads to the high local accumulation of energy in the polarized dielectric medium. The chaotic destabilization events between 2 and 3 stages (rapid detrapping/spl hArr/restoration of space charge) release this energy via strong mechanical relaxation and, as a consequence, form a leakage channel (area less than 10/sup -11/ cm/sup 2/). Thus, the second stage of degradation chain-SLDP (self-localization of degradation process)-plays a crucial role in oxide reliability. The main result of this work-SLDP Model, allowing to explain non-linear decrease of substrate hole current (DSHC effect), which was observed in small MOS structures, subjected to stresses caused by electron injection. It is also shown that the most popular degradation/breakdown models are inapplicable for interpretation of DSHC effect. The presence of local SiO/sub 2/ regions, resistant to the negative space charge formation (endurance up to 10/sup 4/ A/cm/sup 2/ and 10/sup 4/ Cl/cm/sup 2/), allows us to explain a positive feedback of SLDP. Temperature analysis strongly supports new degradation/breakdown model and models which involve hydrogen related effects in oxide films under the field/temperature stress.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130591741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
True low-voltage flash memory operations 真正的低压闪存操作
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534678
M. Chi, A. Bergemont
{"title":"True low-voltage flash memory operations","authors":"M. Chi, A. Bergemont","doi":"10.1109/NVMT.1996.534678","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534678","url":null,"abstract":"This paper proposes true low-voltage operations for high-performance flash memory. The program and erase operations only need voltages not exceeding the junction breakdown voltage of CMOS technology. In this way, flash memory is easily integrated with CMOS logic circuits, since there is no special fabrication process for high-voltage junctions, gate oxide, and field isolation. Low-voltage programming is based on hot electron injection with Vcc on drain and gate. Low-voltage erase is based on Fowler-Nordheim (F-N) tunneling with negative gate bias and Vcc on source and careful grounding the n-well for negative voltage circuits. Low-voltage read operation is seriously degraded using conventional one-transistor (1T) cell due to reduced read current by low gate bias and not allowing operation in depletion. A 2-transistor (2T) cell structure is proposed for high speed read at low Vcc by allowing cell operation in depletion, precharging the cell gate, and switching the select transistor by Vcc. This scheme greatly simplifies the cost of integrating flash memory with logic circuits and is promising for future high-performance systems with low-voltage and low-power applications.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124530783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microfile-a one-inch disk drive technology demonstration 微文件-一英寸磁盘驱动器技术演示
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534662
T. Reiley, T. Albrecht, M. A. Moser, O. Ruiz, S. Pattanaik, H. Tzeng, L. Fan, F.C. Lee, C. C. Chieng
{"title":"Microfile-a one-inch disk drive technology demonstration","authors":"T. Reiley, T. Albrecht, M. A. Moser, O. Ruiz, S. Pattanaik, H. Tzeng, L. Fan, F.C. Lee, C. C. Chieng","doi":"10.1109/NVMT.1996.534662","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534662","url":null,"abstract":"As the areal data density in magnetic storage continues to grow at a rapid pace (/spl sim/50%/yr), small form factor disk drives become increasingly viable. For certain applications, such as cameras or communication devices, where storage capacity requirements are low (/spl sim/50-200 MB), and where small size, low power consumption and high shock resistance are important, very small disk drives may prove attractive, especially given the current and projected cost differential between magnetic storage and semiconductor storage. As a joint effort between IBM Research and IBM Storage Systems Division, a technology demonstration of a miniature disk drive, called Microfile, has been completed. The Microfile has a single 24 mm disk and two MR heads, with a capacity, using 1996 head/disk technology, of 100 MB. The majority of the mechanical components are miniature versions of conventional designs; however several key components-suspension, flex cable, and actuator coil-have been integrated into a single planar suspension assembly. The sliders have a modified air bearing design to accommodate the relatively low linear velocity. A novel simplified host interface (IEEE P1285) is a low cost option under consideration for use in systems with limited requirements. Functional mechanical prototypes have been constructed, and magnetic read/write capability has been demonstrated. Aspects of the Microfile design and fabrication are described.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129255644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of flash memory for use in low earth orbit 快闪存储器在近地轨道上的应用
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534689
Hyeong Park, E. Anderson
{"title":"Application of flash memory for use in low earth orbit","authors":"Hyeong Park, E. Anderson","doi":"10.1109/NVMT.1996.534689","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534689","url":null,"abstract":"Summary form only given. SEAKR engineering has developed a non-volatile solid state recorder for NASA Goddard Space Flight Center. Review of available NV memory technologies at the time (1994) showed that semiconductor flash memory provided the best mixture of density, availability, reliability, and radiation tolerance. A Gbit recorder was delivered to NASA GSFC in June 1995 and will orbit in April 1996 on STS-77's Spartan Satellite mission. The authors present a memory trade study, rationale for selection of flash, radiation test results and orbital flight status.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flash memories: a review 闪记忆:回顾
Proceedings of Nonvolatile Memory Technology Conference Pub Date : 1996-06-24 DOI: 10.1109/NVMT.1996.534690
M. Gill
{"title":"Flash memories: a review","authors":"M. Gill","doi":"10.1109/NVMT.1996.534690","DOIUrl":"https://doi.org/10.1109/NVMT.1996.534690","url":null,"abstract":"Summary form only given. Many approaches are being used to manufacture or develop flash memory products to meet various market needs. These approaches can be classified broadly according to programming mechanism: channel hot electron (including source-side injection) and Fowler-Nordheim tunnelling. Some of the technologies in manufacturing or in development are: NOR stack gate, split gate, source-side injection NAND, DINOR, AND. In addition, a host of technologies for embedded flash applications are in different stages of development. Multi-level cell technologies are being developed to reduce cost/bit. 3-D structures are being investigated to realize small cell size. This paper reviews the different memory technologies, principles of operation, the status, the tradeoffs in cost, performance and reliability. It also discusses emerging flash technologies to serve industrial and next generation consumer electronic products including low voltage, low power portable and mobile devices.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信