{"title":"具有两位存储容量的双门EEPROM单元","authors":"M. Lorenzini, M. Rudan, G. Baccarani","doi":"10.1109/NVMT.1996.534676","DOIUrl":null,"url":null,"abstract":"In this paper, a dual-gate flash EEPROM cell is proposed which allows the storage of two bits at the expense of a slight increase in cell size. Extensive simulations show that the basic functions of the flash cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. A simplified model based on the equivalent circuit of the cell allows a qualitative interpretation of the obtained results, and is of great help for the optimization of the cell parameters.","PeriodicalId":391958,"journal":{"name":"Proceedings of Nonvolatile Memory Technology Conference","volume":"151 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A dual gate flash EEPROM cell with two-bits storage capacity\",\"authors\":\"M. Lorenzini, M. Rudan, G. Baccarani\",\"doi\":\"10.1109/NVMT.1996.534676\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a dual-gate flash EEPROM cell is proposed which allows the storage of two bits at the expense of a slight increase in cell size. Extensive simulations show that the basic functions of the flash cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. A simplified model based on the equivalent circuit of the cell allows a qualitative interpretation of the obtained results, and is of great help for the optimization of the cell parameters.\",\"PeriodicalId\":391958,\"journal\":{\"name\":\"Proceedings of Nonvolatile Memory Technology Conference\",\"volume\":\"151 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Nonvolatile Memory Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMT.1996.534676\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Nonvolatile Memory Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.1996.534676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dual gate flash EEPROM cell with two-bits storage capacity
In this paper, a dual-gate flash EEPROM cell is proposed which allows the storage of two bits at the expense of a slight increase in cell size. Extensive simulations show that the basic functions of the flash cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. A simplified model based on the equivalent circuit of the cell allows a qualitative interpretation of the obtained results, and is of great help for the optimization of the cell parameters.