A low voltage SONOS nonvolatile semiconductor memory technology

Abstract

The triple dielectric SONOS (polysilicon-blocking oxide-silicon nitridetunnel oxide-silicon) structure is an attractive candidate for high density E/sup 2/PROM's suitable for semiconductor disks and a replacement for high-density DRAMS. Low programming voltages (5 V) and high endurance (greater than 10/sup 7/ cycles) are possible in this multi-dielectric technology as the intermediate Si/sub 3/N/sub 4/ layer is scaled to thicknesses of 50 A. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and as associated CMOS peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F/sup 2/, where F is the technology feature size. A 0.20 /spl mu/m feature size permits a 1TC area of 0.24 /spl mu/m/sup 2/ for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.