2009 International Conference on Microelectronics - ICM最新文献

{"title":"Activation of shallow B and BF2 implants in Si using Excimer laser annealing","authors":"Z. Ali-Guerry, M. Marty, R. Beneyton, N. Moussy, J. Venturini, K. Huet, G. Lu, D. Dutartre","doi":"10.1109/ICM.2009.5418601","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418601","url":null,"abstract":"We have used laser thermal annealing (LTA) to activate shallow B and BF2 implants in p-type SOI wafers. Several characterization techniques have been employed in our investigations, such as SiPHER photoluminescence (PL) scans, Sheet resistance measurements (Rs), SIMS and AFM analyses. In sub-melt regime, there is no significant redistribution of implanted dopants; furthermore, BF2 implanted sample exhibits lower boron activation compared with B implanted one. In melt regime, a characteristic box-like doping profile appears, with a depth corresponding to the melting depth controllable by LTA energy setting. However, at a given annealing energy, BF2-implanted Si has a larger melting depth than the B-implanted one. In both cases, a dramatic enhancement in defect curing (PL Increase) and in dopants activation (Rs decrease) has been observed on melting. On the other hand, surface roughness is suddenly increased with the appearance of peaks in surface morphology around the melting threshold.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131217574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling of active compensated KHN band pass filter using standard hardware description language","authors":"Rasha E. El-Queseny, S. Mahmoud, M. Ibrahim","doi":"10.1109/ICM.2009.5418583","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418583","url":null,"abstract":"This research paper models the Kerwin Huelsman Newcomb (KHN) band pass filter [1] using standard hardware description language (VHDL). The illustrated modeling approach allows simulating analog building blocks using a language used for describing digital hardware. Simulation results using the proposed VHDL model of the KHN filter for both in time and frequency are given. PSPICE simulation results confirm the VHDL simulation results are also given.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126951076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Kink reduction using selective back oxide structure","authors":"M. Narayanan, H. Al-Nashash, B. Mazhari, D. Pal","doi":"10.1109/ICM.2009.5418610","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418610","url":null,"abstract":"This paper describes a method for reducing the kink effect observed in the I-V output characteristics of a partially depleted SOI MOSFETs. It involves the use of back oxide below drain and source and also below part of the channel. Silvaco TCAD tools are used for fabrication and device simulation. Basic mechanism leading to the generation of kink in SOI MOS devices is studied. Effect of selective back oxide structure with various gap widths and thicknesses help to eliminate the kink effect is also verified. Results obtained through numerical simulations indicated that Kink can be significantly reduced with the use of Selective Back Oxide Structure while preserving the major advantages offered by the conventional SOI structure.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116058986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of nanometer MOS Current Mode Logic: From very high-speed down to ultra-low power","authors":"M. Alioto","doi":"10.1109/ICM.2009.5418674","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418674","url":null,"abstract":"In the last years, MOS Current-Mode Logic (MCML) circuits have become very popular in a wide range of applications, from high-accuracy mixed-signal circuits to very high-speed circuits, and very recently for ultra-low power circuits. In MCML circuits, desirable features come at the cost of static power consumption, hence power-aware design techniques are needed. At the same time, issues related to the high complexity of current circuits (e.g., design automation) and nanometer technologies (e.g., variability) must be explicitly taken into account in real designs. In this tutorial, a survey of fresh ideas and recent techniques to design MCML circuits is presented. Concepts are introduced in a design perspective and cover multiple levels of abstraction, ranging from transistor to system. A comparison with CMOS logic is presented to identify the applications where MCML exhibit better features. Models for MCML circuits in nanometer CMOS technologies are presented and then used to derive power-aware design guidelines and criteria for a wide variety of applications. Since commercial CAD tools do not explicitly support differential logic styles, issues related to the CADbased automated design of complex circuits are discussed, and recently proposed solutions are reviewed. Guidelines are developed to design standard cells and perform automated synthesis and place & route with standard tools. Design criteria for area-power efficient differential routing are also given. Variability issues are explicitly dealt with and considered from the beginning, rather than as an afterthought. System-level biasing schemes to dynamically control the power-speed tradeoff and compensate variations are discussed for a wide range of applications, from very high speed to ultra-low power. MCML gates are also shown to be better suited for ultra-low power operation (e.g., to implement the digital processing unit in wireless sensor nodes), compared to CMOS logic. Design issues arising in the ultralow power realm with a power consumption in the order of pW-per-gate are discussed, and appropriate circuit techniques to allow reliable operation are presented. Limits to ultra-low power operation are analyzed by evaluating the minimum supply voltage that is allowed in MCML circuits, and recent body biasing techniques to push down this voltage limit are discussed. The impact of process/voltage/temperature variations is extensively analyzed to understand the intrinsic advantages of MCML circuits in ultra-low power circuits, and design strategies to counteract power-delay variations are presented. Finally, open questions and aspects that require further investigation are discussed, and new directions for the foreseeable future are proposed.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121402289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High frequency OTA-C filters with current and voltage transfer functions based on multiple loop feedback technique","authors":"Mona ElGuindy, E. Soliman, S. Mahmoud","doi":"10.1109/ICM.2009.5418602","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418602","url":null,"abstract":"This paper addresses the analysis of three different fourth order low pass filters at cutoff frequency of 10MHz. The filters are realized using: the inverse follow-the-leader-feedback (IFLF), the leap frog (LF), and cascaded multiple loop feedback (MLF) operational transconductor amplifier-capacitor (OTA-C) filters with voltage and current transfer functions. A CMOS OTA cell proposed in [1] is used to realize the three filters. PSPICE simulations are done using 0.25µm model and supply voltage of ±2.5V. A comparison between the different filters proved that the current transfer function filters have a lower cutoff frequency error between the theoretical and simulation values, and a lower output referred noise density under 1KΩ load by a factor of 10−3. The voltage transfer function has the advantage of having a lower group delay than that of the current transfer function filters.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125528066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based multispectral fluorometer using CDMA and embedded neural network","authors":"M. Boukadoum, A. Trabelsi, C. Fayomi","doi":"10.1109/ICM.2009.5418652","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418652","url":null,"abstract":"We report on the design and implementation of a fluorescence measurement and analysis device that can identify fluorophore substances. The device performs multi-spectral fluorescence measurements, obtained by exciting the unknown substance with light emitting diodes (LED) whose intensity is CDMA coded for noise rejection. The acquired fluorescence data are processed by a CDMA receiver and a neural network for spectral signature identification and measurement. The design's front end exploits the capability of color LEDs to act as photodetectors with different spectral responses when reverse-biased. The system avoids using optical lenses and is implemented as a minimum chip count design where an FPGA performs all of the required processing with the exception of the analog front end. It is thus appropriate for field use.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126155518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high-speed processor for finely-spaced Fourier transform via chirp z-transform","authors":"Giuseppe Gentile, M. Rovini, L. Fanucci","doi":"10.1109/ICM.2009.5418585","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418585","url":null,"abstract":"This paper deals with the design of a processor for very-finely spaced spectral analysis over a narrow band of the available spectrum. The processor implements the chirp z-transform (CZT) algorithm, and exploits a fully-parallel architecture in order to address real-time applications with very-high throughput. The internal data-path is optimized as a trade-off between fixed-point accuracy and implementation complexity. The proposed architecture has been customized for the case study of a 64-point transform in a sub-band of 10% of the available spectrum, and has reached the astonishing throughput of 3.2 Gs/s on a Xilinx Virtex-IV FPGA. Also, compared with a customary approach based on FFT, a remarkable saving in complexity is shown.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal challenges to gate length reduction of FET","authors":"A. Darwish, H. A. Hung","doi":"10.1109/ICM.2009.5418612","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418612","url":null,"abstract":"The constant need for higher speed continues to lead to devices with shorter gate lengths, smaller gate widths, and gate finger spacing. The relationship of between various transistor parameters and the device lifetime is unclear due to the complexity of the problem, and the difficulty and expense of measuring reliability. This paper presents an analytical expression relating the reliability to a field effect transistor's (FET) gate length, based on thermal considerations. Experimental observations support the model's conclusions.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Different baseband chain architectures for multi-standard reconfigurable receivers","authors":"M. A. Dawoud, S. Mahmoud, A. K. Kafrawy","doi":"10.1109/ICM.2009.5418657","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418657","url":null,"abstract":"In this paper different baseband chain architectures used in multi-standard reconfigurable receivers are proposed. The architectures are simulated using CMOS 0.25μιη technology operating with 1.2V supply voltage. Performance comparisons between different architectures demonstrate the optimum baseband requirements for a multi-standard receiver in terms of DC-Gain, noise, linearity, SFDR, and power consumption.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124003342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and evaluation of layout density of FinFET logic gates","authors":"M. Alioto","doi":"10.1109/ICM.2009.5418680","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418680","url":null,"abstract":"In this paper, the layout density of FinFET logic gates is analyzed and compared to that of bulk CMOS logic. Analysis starts from basic structures, including single- and multi-finger transistors, as well as stacked transistors. As opposite to previous work, four-terminal (4T) FinFETs are also explicitly taken into account. The analysis is extended to the physical design of a standard cell library in 65-nm technology. Comparison with bulk technology confirms that 3T FinFETs suffer from significant layout density degradation, as was previously observed in [1]. Moreover, it is shown that 4T FinFETs have a considerably worse layout density, compared to 3T FinFETs and bulk transistors. The sources of the 3T-4T layout density degradation are also discussed. Finally, the mixed 3T-4T approach, which was recently proposed to reduce the leakage power, is investigated as a compromise between 3T and 4T FinFET circuits in terms of area.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}