Analysis and evaluation of layout density of FinFET logic gates

Abstract

In this paper, the layout density of FinFET logic gates is analyzed and compared to that of bulk CMOS logic. Analysis starts from basic structures, including single- and multi-finger transistors, as well as stacked transistors. As opposite to previous work, four-terminal (4T) FinFETs are also explicitly taken into account. The analysis is extended to the physical design of a standard cell library in 65-nm technology. Comparison with bulk technology confirms that 3T FinFETs suffer from significant layout density degradation, as was previously observed in [1]. Moreover, it is shown that 4T FinFETs have a considerably worse layout density, compared to 3T FinFETs and bulk transistors. The sources of the 3T-4T layout density degradation are also discussed. Finally, the mixed 3T-4T approach, which was recently proposed to reduce the leakage power, is investigated as a compromise between 3T and 4T FinFET circuits in terms of area.