Different baseband chain architectures for multi-standard reconfigurable receivers

Abstract

In this paper different baseband chain architectures used in multi-standard reconfigurable receivers are proposed. The architectures are simulated using CMOS 0.25μιη technology operating with 1.2V supply voltage. Performance comparisons between different architectures demonstrate the optimum baseband requirements for a multi-standard receiver in terms of DC-Gain, noise, linearity, SFDR, and power consumption.