Design of nanometer MOS Current Mode Logic: From very high-speed down to ultra-low power

Abstract

In the last years, MOS Current-Mode Logic (MCML) circuits have become very popular in a wide range of applications, from high-accuracy mixed-signal circuits to very high-speed circuits, and very recently for ultra-low power circuits. In MCML circuits, desirable features come at the cost of static power consumption, hence power-aware design techniques are needed. At the same time, issues related to the high complexity of current circuits (e.g., design automation) and nanometer technologies (e.g., variability) must be explicitly taken into account in real designs. In this tutorial, a survey of fresh ideas and recent techniques to design MCML circuits is presented. Concepts are introduced in a design perspective and cover multiple levels of abstraction, ranging from transistor to system. A comparison with CMOS logic is presented to identify the applications where MCML exhibit better features. Models for MCML circuits in nanometer CMOS technologies are presented and then used to derive power-aware design guidelines and criteria for a wide variety of applications. Since commercial CAD tools do not explicitly support differential logic styles, issues related to the CADbased automated design of complex circuits are discussed, and recently proposed solutions are reviewed. Guidelines are developed to design standard cells and perform automated synthesis and place & route with standard tools. Design criteria for area-power efficient differential routing are also given. Variability issues are explicitly dealt with and considered from the beginning, rather than as an afterthought. System-level biasing schemes to dynamically control the power-speed tradeoff and compensate variations are discussed for a wide range of applications, from very high speed to ultra-low power. MCML gates are also shown to be better suited for ultra-low power operation (e.g., to implement the digital processing unit in wireless sensor nodes), compared to CMOS logic. Design issues arising in the ultralow power realm with a power consumption in the order of pW-per-gate are discussed, and appropriate circuit techniques to allow reliable operation are presented. Limits to ultra-low power operation are analyzed by evaluating the minimum supply voltage that is allowed in MCML circuits, and recent body biasing techniques to push down this voltage limit are discussed. The impact of process/voltage/temperature variations is extensively analyzed to understand the intrinsic advantages of MCML circuits in ultra-low power circuits, and design strategies to counteract power-delay variations are presented. Finally, open questions and aspects that require further investigation are discussed, and new directions for the foreseeable future are proposed.