Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.最新文献

Hot carrier reliability of HfSiON NMOSFETs with poly and TiN metal gate 具有聚锡金属栅极的HfSiON nmosfet的热载流子可靠性

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367802

J. Sim, B. Lee, R. Choi, K. Matthews, D. Kwong, L. Larson, P. Tsui, G. Bersuker

{"title":"Hot carrier reliability of HfSiON NMOSFETs with poly and TiN metal gate","authors":"J. Sim, B. Lee, R. Choi, K. Matthews, D. Kwong, L. Larson, P. Tsui, G. Bersuker","doi":"10.1109/DRC.2004.1367802","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367802","url":null,"abstract":"High-k dielectrics have been proposed to replace SiO/sub 2/ to reduce gate leakage current. Among reliability concerns of the hafnium based metal oxides (Y.H. Kim et al., Tech. Dig. of IEDM, p. 861, 2002) hot carrier effects may represent one of the major limitations for the high-k gate dielectrics introduction (Q. Lu et al., IRPS, p.429, 2002; A. Kumar, VLSI, p. 152, 2003). However, most of the studies did not take into consideration that the hot carriers-induced degradation might be accompanied by the electron trapping in the bulk of the high-k film (C.D. Young et al., IRW, p. 28, 2003) due to the high density of structural defects in the high-k dielectrics (G. Bersuker et al., Materials Today, vol. 26, Jan. 2004). This bulk electron trapping, which is not observed in the case of SiO/sub 2/ dielectrics, can significantly affect transistor parameters and, therefore, complicates evaluation of hot carrier degradation properties of the high-k gate stacks. In this paper, we investigate test conditions for the hot carrier stress of the poly and TiN gate NMOSFETs with HfSiON gate dielectric that would more accurately address the above issues.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Effect of gate recessing on linearity characteristics of AlGaN/GaN HEMTs 栅极凹陷对AlGaN/GaN hemt线性特性的影响

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367770

A. Chini, D. Buttari, R. Coffie, L. Shen, T. Palacios, S. Heikman, A. Chakraborty, S. Keller, U. Mishra

引用次数: 4

An organic thin-film transistor with photolithographically patterned top contacts and active layer 一种有机薄膜晶体管，具有光刻图案的顶部触点和有源层

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367794

G. Gu, M. Kane, J. Doty, A. Firester

引用次数: 3

Optical near-field enhancement of metal-aperture VCSEL with nano metal particle 纳米金属颗粒对金属孔径VCSEL光学近场增强研究

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367833

J. Hashizume, F. Koyama

引用次数: 0

C/sub bc/ reduction in InP heterojunction bipolar transistor with selectively implanted collector pedestal 选择性植入集电极基座的InP异质结双极晶体管的C/sub / bc/降低

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367786

Yingda Dong, Z. Griffith, M. Dahlstrom, M. Rodwell

{"title":"C/sub bc/ reduction in InP heterojunction bipolar transistor with selectively implanted collector pedestal","authors":"Yingda Dong, Z. Griffith, M. Dahlstrom, M. Rodwell","doi":"10.1109/DRC.2004.1367786","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367786","url":null,"abstract":"The base-collector junction capacitance (C/sub bc/) is a key factor limiting HBT high frequency performance. To reduce C/sub bc/, we report an HBT structure with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth, the first such structure reported in III-V HBTs. It is designed so that the depleted collector thickness in HBT's extrinsic region is much larger than the depleted collector thickness in HBT's intrinsic region, and therefore substantially reducing the extrinsic base-collector capacitance. Although C/sub bc/ can also be reduced by forming a narrow N+ subcollector stripe lying under the emitter (M. Sokolich et al., 25th IEEE GaAsIC Symp.), such structures can have large collector access resistance Rc arising from long, narrow N+ layer. The collector pedestal structure, however, does not significantly increase collector access resistance relative to a standard mesa structure, and is consequently the approach most widely employed in Si/SiGe technology. We had earlier reported collector pedestal HBTs with low leakage and good DC characteristics (Y. Dong et al., Proc. 2003 Int. Semicond. Dev. Res. Symp., pp. 348-349, 2003); here we report devices with the expected large reduction in C/sub bc/.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Channel confined kinesin-microtubule biomolecular nanomotors 通道受限动力-微管生物分子纳米马达

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367852

Y.M. Huang, M. Uppalapati, W. Hancock, T. Jackson

引用次数: 0

An 8V organic complementary logic process for flexible polymeric substrates 柔性聚合物基板的8V有机互补逻辑工艺

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367880

H. Klauk, M. Halik, U. Zschieschang, F. Eder, G. Schmid, C. Dehm

引用次数: 1

Solution processed OTFTs with 1 cm/sup 2//V-s mobility 溶液处理OTFTs具有1 cm/sup 2/ V-s的迁移率

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367900

C. Kuo, M. Payne, J. Anthony, T. Jackson

引用次数: 2

Overgrown Si/SiGe resonant interband tunnel diodes for integration with CMOS 用于集成CMOS的过度生长Si/SiGe谐振带间隧道二极管

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367807

S. Sudirgo, R. Vega, R. P. Nandgaonkar, K. Hirschman, S. Rommel, S. Kurinec, P. Thompson, Niu Jin, P. R. Berger

{"title":"Overgrown Si/SiGe resonant interband tunnel diodes for integration with CMOS","authors":"S. Sudirgo, R. Vega, R. P. Nandgaonkar, K. Hirschman, S. Rommel, S. Kurinec, P. Thompson, Niu Jin, P. R. Berger","doi":"10.1109/DRC.2004.1367807","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367807","url":null,"abstract":"The incorporation of tunnel diodes with field effect transistors (FET) can improve the speed and power capability in electronic circuitry. This has been realized in III-V materials by demonstrating a low power refresh-free tunneling-SRAM and high performance compact A/D converter. A new thrust to integrate tunnel diodes with the mainstream CMOS technology led to the invention of Si/SiGe resonant interband tunnel diode (RITD) (S.L. Rommel et al., Appl. Phys. Lett., vol. 73, pp. 2191-93, 1998) with the highest reported peak-to-valley current ratio (PVCR) of 6.0 (K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001). The structure consists of a SiGe spacer i-layer sandwiched between two delta-doped planes grown by low-thermal molecular beam epitaxy (LT-MBE) (N. Jin et al., IEEE Trans. Elec. Dev., vol. 50, pp. 1876-1884, 2003). By adjusting the spacer layer thickness, the peak current density (Jp) can be adjusted from 0.1 A/cm/sup 2/ up to 151 kA/cm/sup 2/ (N. Jin et al., App. Phys. Lett., 83, pp. 3308-3310, 2003). Recently, monolithic integration of RITD with CMOS has been realized, demonstrating a low-voltage operation of a monostable-bistable logic element (MOBILE) (S.Sudirgo et al., Proc. 2003 Int. Semic. Dev. Res. Symp., pp. 22, 2003). In this study, RITD layers were grown through openings in a 300 nm thick chemical vapor deposition (CVD) SiO/sub 2/ layer.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Directly lithographic top contacts for pentacene organic thin-film transistors 五苯有机薄膜晶体管的直接平版印刷顶触点

Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC. Pub Date : 2004-06-21 DOI: 10.1109/DRC.2004.1367795

C. Kuo, T. Jackson

引用次数: 2