C/sub bc/ reduction in InP heterojunction bipolar transistor with selectively implanted collector pedestal

The base-collector junction capacitance (C/sub bc/) is a key factor limiting HBT high frequency performance. To reduce C/sub bc/, we report an HBT structure with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth, the first such structure reported in III-V HBTs. It is designed so that the depleted collector thickness in HBT's extrinsic region is much larger than the depleted collector thickness in HBT's intrinsic region, and therefore substantially reducing the extrinsic base-collector capacitance. Although C/sub bc/ can also be reduced by forming a narrow N+ subcollector stripe lying under the emitter (M. Sokolich et al., 25th IEEE GaAsIC Symp.), such structures can have large collector access resistance Rc arising from long, narrow N+ layer. The collector pedestal structure, however, does not significantly increase collector access resistance relative to a standard mesa structure, and is consequently the approach most widely employed in Si/SiGe technology. We had earlier reported collector pedestal HBTs with low leakage and good DC characteristics (Y. Dong et al., Proc. 2003 Int. Semicond. Dev. Res. Symp., pp. 348-349, 2003); here we report devices with the expected large reduction in C/sub bc/.