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MC-CDMA/VSF for the downlink physical layer in next generation wireless local area networks 下一代无线局域网下行物理层的MC-CDMA/VSF
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363053
C.A. Gutierrez Diaz de Leon, J.S. Garcia, M.C. Bean, L.A.G.D. de Leon
{"title":"MC-CDMA/VSF for the downlink physical layer in next generation wireless local area networks","authors":"C.A. Gutierrez Diaz de Leon, J.S. Garcia, M.C. Bean, L.A.G.D. de Leon","doi":"10.1109/SIPS.2004.1363053","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363053","url":null,"abstract":"In this paper, a new physical layer for the downlink in future generation wireless local area networks (WLANs), operating in the ISM band, and based on multi-carrier CDMA (MC-CDMA) is proposed. Taking advantage of the CDMA properties, this physical layer aims to provide service simultaneously to several users with different data rate needs. Orthogonal variable spreading factor (OVSF) codes are employed in order to support the simultaneous coexistence of different data rate users. In addition, the bit error rate (BER) performance of the system is analyzed for different combination techniques when single-user detection is employed in a frequency selective slow fading Rician channel. According to the results presented in this paper, this proposal is a promising option for WLANs.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129575045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363036
Michael J. Meeuwsen, Omar Sattari, B. Baas
{"title":"A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter","authors":"Michael J. Meeuwsen, Omar Sattari, B. Baas","doi":"10.1109/SIPS.2004.1363036","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363036","url":null,"abstract":"A software based IEEE 802.11a digital baseband transmitter has been implemented on a highly parallel single-chip DSP. The processing platform is a programmable and reconfigurable asynchronous array of simple processors (AsAP) that is well matched to complex system workloads such as 802.11a. The transmitter is the first fully-compliant 802.11a software implementation, and is the first full-rate software implementation. The transmitter also complies with the high-rate portions of the 802.11g standard. It operates over all 8 data rates, includes additional upsampling and filtering functions, and sustains transmissions at 54 Mb/s on a 22-processor array; it is expected to occupy less than 20 mm/sup 2/ in 0.18 /spl mu/m CMOS.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems 功率感知视频编码系统的多模式内容感知运动估计算法
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363056
Siou-Shen Lin, Po-Chih Tseng, Chia-Ping Lin, Liang-Gee Chen
{"title":"Multi-mode content-aware motion estimation algorithm for power-aware video coding systems","authors":"Siou-Shen Lin, Po-Chih Tseng, Chia-Ping Lin, Liang-Gee Chen","doi":"10.1109/SIPS.2004.1363056","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363056","url":null,"abstract":"By exploiting the characteristics of the video signal, two content-aware decision criteria are proposed to identify the complexity of motion vectors. Based on these two decision criteria, as well as different combinations of various motion estimation algorithms, four different modes are proposed to allow the computation resources to be varied dynamically between different power constraints. The proposed decision criteria also enable the maximization of quality under each power constraint by a quality-driven diversity-based search approach. According to our simulation results, the proposed algorithm can effectively reduce the computation resources to 40%, 21%, and 3.73% with only 0.0036 dB, 0.01 dB, and 0.16 dB average quality degradation, respectively. As a result, the proposed algorithm is well-suited for video coding systems that desire a power-awareness feature.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128981469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design 基于统一有限域处理单元设计的可扩展Reed-Solomon解码处理器
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363040
Jih-Chiang Yeo, Huai-Yi Hsu, A. Wu
{"title":"A scalable Reed-Solomon decoding processor based on unified finite-field processing element design","authors":"Jih-Chiang Yeo, Huai-Yi Hsu, A. Wu","doi":"10.1109/SIPS.2004.1363040","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363040","url":null,"abstract":"In this paper, we present the design of a scalable Reed-Solomon (RS) codec processor design with a reconfigurable architecture. The reconfigurable architecture has good flexibility for tradeoff between the data throughput rate and power consumption. Compared with the DSP type architecture, the proposed reconfigurable architecture can perform at a higher data throughput rate with shorter latency. Besides, with the combination of two RS processor engines, we can easily double the performance with the scalable design. This good scalability is another advantage of our proposed reconfigurable architecture.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122516826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Memory communication network exploration for low-power distributed memory organisations 低功耗分布式存储器组织的存储器通信网络探索
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363045
A. Papanikolaou, K. Koppenberger, M. Miranda, E. Catthoor
{"title":"Memory communication network exploration for low-power distributed memory organisations","authors":"A. Papanikolaou, K. Koppenberger, M. Miranda, E. Catthoor","doi":"10.1109/SIPS.2004.1363045","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363045","url":null,"abstract":"Minimising the energy consumption due to the data storage and transfer in data-dominated systems is critical for the design of embedded systems. Distributed memory organisations have been proposed as an efficient storage architecture alternative. However, the impact of the interconnect overhead in these has been traditionally neglected, which is not acceptable any more for deep sub-micron technologies. In this paper, we propose combining the exploration of the memory organisation with the exploration of the communication network and highlight its importance compared to the independent local explorations. This combined exploration can provide gains of 30% in the overall energy consumption of both the memory and its interconnection network design methodologies.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124270289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FPGA implementation of an IF transceiver for OFDM-based WLAN 基于ofdm的无线局域网中频收发器的FPGA实现
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363054
M. J. Canet, F. Vicedo, V. Almenar, J. Valls
{"title":"FPGA implementation of an IF transceiver for OFDM-based WLAN","authors":"M. J. Canet, F. Vicedo, V. Almenar, J. Valls","doi":"10.1109/SIPS.2004.1363054","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363054","url":null,"abstract":"The paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for the HIPERLAN/2 standard, but most of the work can be generalized to IEEE 802.11a/g standards. The system is composed of three main blocks (autocorrelator, CORDIC, and FFT processor) that are used in different time intervals to perform all the required operations. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is reused to estimate frequency offset, to compensate that frequency and to calculate the division in the channel estimation stage. Finally, the FFT/IFFT processor also uses its complex-number multiplier to perform the channel compensation of the received OFDM symbols. The whole IF transceiver fits in a low cost FPGA, an XC3S400-4 Spartan III device.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131545512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
ELMMA: a new low power high-speed adder for RNS ELMMA:一种新的低功耗高速RNS加法器
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363031
R. A. Patel, M. Benaissa, N. Powell, S. Boussakta
{"title":"ELMMA: a new low power high-speed adder for RNS","authors":"R. A. Patel, M. Benaissa, N. Powell, S. Boussakta","doi":"10.1109/SIPS.2004.1363031","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363031","url":null,"abstract":"Modular adders are fundamental arithmetic components that are employed in residue number system (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies, as well as a growing demand for portable electronics, have brought power reduction to the forefront of modern design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. We propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13 /spl mu/m standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay /spl times/ area efficiency when compared to existing modular adder designs in the literature.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125003381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Efficient digital baseline wander algorithm and its architecture for fast Ethernet 快速以太网中高效的数字基线漂移算法及其体系结构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363038
J. Baek, J. Hong, M. Sunwoo, K.U. Kim
{"title":"Efficient digital baseline wander algorithm and its architecture for fast Ethernet","authors":"J. Baek, J. Hong, M. Sunwoo, K.U. Kim","doi":"10.1109/SIPS.2004.1363038","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363038","url":null,"abstract":"The paper proposes an efficient digital baseline wander (BLW) algorithm and its hardware architecture for 100BASE-TX Ethernet. The proposed BLW compensator uses four symbols, including the present symbol, and can remove BLW at the channel having large BLW or having a killing packet. The proposed BLW compensator is purely implemented in a digital domain. To verify the performance of the proposed BLW compensator, we simulate a 100BASE-TX DSP submodule using the SPW/spl trade/ tool. The DSP submodule has been modeled by Verilog-HDL and synthesized using the 0.18 /spl mu/m SEC cell library. The measured BER is less than 10/sup -10/ when the transmitted data is received up to 150 m. The implemented DSP submodule operates at 142.7 MHz and consists of 128,528 gates. Since the 1000Base-T receiver uses DSP submodule similar to 100BASE-TX receiver, the proposed architecture can be reused for gigabit Ethernet.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114426476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
VLSI MAP decoder architectural analysis VLSI MAP解码器架构分析
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363065
M. Elassal, M. Bayoumi
{"title":"VLSI MAP decoder architectural analysis","authors":"M. Elassal, M. Bayoumi","doi":"10.1109/SIPS.2004.1363065","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363065","url":null,"abstract":"This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115595635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A comparative study of the suitability of a custom computing machine and a VLIW DSP for use in 3G applications 在3G应用中使用自定义计算机和VLIW DSP的适用性比较研究
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363047
J. Neel, S. Srikanteswara, J. Reed, P. Athanas
{"title":"A comparative study of the suitability of a custom computing machine and a VLIW DSP for use in 3G applications","authors":"J. Neel, S. Srikanteswara, J. Reed, P. Athanas","doi":"10.1109/SIPS.2004.1363047","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363047","url":null,"abstract":"As wireless communications advances, the complexity of waveform processing places an ever increasing demand on baseband processing resources. As this is a difficult problem for traditional processing solutions to address, many have looked to reconfigurable computing as a solution. For 3G systems, whose intense processing requirements exacerbate these problems, we have previously proposed in (S. Srikanteswara et al, Soft Radio Impl. for 3G and Future High Data Rate Syst., Globecom 2001) the use of custom computing machines (CCMs), also known as adaptive computing machines (ACMs). This paper introduces a method for measuring processor performance which is independent of chip architecture. This method is then used to perform a comparative analysis on the suitability of Virginia Tech's Stallion CCM and Texas, Instrument's TMS320C6201 processor for use in 3G applications.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130159347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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