A scalable Reed-Solomon decoding processor based on unified finite-field processing element design

Abstract

In this paper, we present the design of a scalable Reed-Solomon (RS) codec processor design with a reconfigurable architecture. The reconfigurable architecture has good flexibility for tradeoff between the data throughput rate and power consumption. Compared with the DSP type architecture, the proposed reconfigurable architecture can perform at a higher data throughput rate with shorter latency. Besides, with the combination of two RS processor engines, we can easily double the performance with the scalable design. This good scalability is another advantage of our proposed reconfigurable architecture.