{"title":"VLSI MAP解码器架构分析","authors":"M. Elassal, M. Bayoumi","doi":"10.1109/SIPS.2004.1363065","DOIUrl":null,"url":null,"abstract":"This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"247 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"VLSI MAP decoder architectural analysis\",\"authors\":\"M. Elassal, M. Bayoumi\",\"doi\":\"10.1109/SIPS.2004.1363065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.\",\"PeriodicalId\":384858,\"journal\":{\"name\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"volume\":\"247 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2004.1363065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2004.1363065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents an architectural analysis for MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
