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High-performance adaptive GPS attitude determination VLSI architecture 高性能自适应GPS姿态确定VLSI结构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363055
E. F. Stefatos, T. Arslan
{"title":"High-performance adaptive GPS attitude determination VLSI architecture","authors":"E. F. Stefatos, T. Arslan","doi":"10.1109/SIPS.2004.1363055","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363055","url":null,"abstract":"The paper presents an adaptive VLSI hardware architecture for an attitude determination system (ADS), which is based on Global Positioning System (GPS) measurements. The system composes the digital core of a GPS receiver, which manipulates the input data in order to resolve the attitude of a vehicle. The adaptation of this architecture is achieved by using a fine-grained parallel genetic algorithm (PGA) that is employed to compute more efficiently the attitude determination algorithm in terms of speed performance. The PGA consists of 64 processing elements (PEs), which are connected in the formation of an 8/spl times/8 array. Moreover, the hardware block that computes the fitness function of the PGA employs coordinate rotation digital computer (CORDIC) algorithms in order to increase the throughput rate of the ADS further.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Data wordlength reduction for low-power signal processing software 用于低功耗信号处理软件的数据字长缩减
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363074
Kyungtae Han, Brian L. Evans, E. Swartzlander
{"title":"Data wordlength reduction for low-power signal processing software","authors":"Kyungtae Han, Brian L. Evans, E. Swartzlander","doi":"10.1109/SIPS.2004.1363074","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363074","url":null,"abstract":"Reducing power consumption prolongs battery life and increases integration. In digital CMOS designs, switching activity is closely connected with the total power consumption. Switching activity on programmable processors implementing linear filters, fast Fourier transforms, and other signal processing operations is dominated by the hardware multiplier. In this paper, we employ wordlength reduction of multiplicands to reduce switching activity in hardware multipliers using truncation and signed right shift methods. For 32 bit /spl times/ 32 bit Wallace and radix-4 modified Booth multipliers, truncation by 16 bits achieves a 4:1 and 2:1 reduction, respectively, in switching activity, whereas signed right shift gives little or no reduction. The key contribution of this paper is the reduction of power consumption by altering multiplicands in software without any hardware modifications.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Rate control using enhanced frame complexity measure for H.264 video 基于增强帧复杂度度量的H.264视频速率控制
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363060
Xiaoquan Yi, N. Ling
{"title":"Rate control using enhanced frame complexity measure for H.264 video","authors":"Xiaoquan Yi, N. Ling","doi":"10.1109/SIPS.2004.1363060","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363060","url":null,"abstract":"Bit rate control is an important issue for wireless and Internet video streaming. The paper presents a revised rate control scheme based on an improved frame complexity measure. Rate control adopted by both MPEG-4 VM18 and H.264/AVC uses a quadratic rate-distortion (R-D) model that determines quantization parameters (QPs). The classical quadratic R-D model is suitable for MPEG-4, but it performs poorly for H.264/AVC because one of the important parameters, mean absolute difference (MAD), is predicted through a linear model, whereas the MAD used in MPEG-4 VM18 is the actual MAD. Inaccurately predicted MAD results in the wrong QP and consequently degrades rate distortion optimization (RDO) performance in H.264/AVC. To overcome the limitation of the existing rate control schemes, we introduce an enhanced linear model for predicting MAD, utilizing some knowledge of current frame complexity. Moreover, we propose a more accurate frame complexity measure, namely, normalized MAD, to replace the current use of MAD parameters. Normalized MAD has a stronger correlation with optimally allocated bits than that of the predicted MAD. Finally, a dynamic bit allocation scheme among basic units is implemented. Extensive simulation results show that our method, with inexpensive added computational complexity, improves the average peak signal-to-noise ratio (PSNR) considerably, by up to 1.2 dB, and reduces PSNR variances significantly, by up to 63%.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Fault-tolerant computation within complex FIR filters 复杂FIR滤波器中的容错计算
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363069
P. Chan, G. Jullien, L. Imbert, V. Dimitrov, G. McGibney
{"title":"Fault-tolerant computation within complex FIR filters","authors":"P. Chan, G. Jullien, L. Imbert, V. Dimitrov, G. McGibney","doi":"10.1109/SIPS.2004.1363069","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363069","url":null,"abstract":"In this paper we propose an architecture for the implementation of fault-tolerant computation within a high throughput multirate equalizer for all asymmetrical wireless LAN. The area overhead is minimized by exploiting the algebraic structure of the modulus replication residue number system (MRRNS). We demonstrate that for our system the area cost to correct a fault in a single computational channel is 82.7%. Generalized results for single error correction showing significant area savings are also presented.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133723410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Extended instructions for the AES cryptography and their efficient implementation AES密码学的扩展指令及其有效实现
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363041
K. Nadehara, M. Ikekawa, Ichiro Kuroda
{"title":"Extended instructions for the AES cryptography and their efficient implementation","authors":"K. Nadehara, M. Ikekawa, Ichiro Kuroda","doi":"10.1109/SIPS.2004.1363041","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363041","url":null,"abstract":"In this paper, extended instructions for the advanced encryption standard (AES) cryptography acceleration in embedded processors and efficient implementation of these instructions are presented. These AES instructions generate four elements in single-instruction, multiple-data format from each input of an AES state. The instruction count for 128-bit key AES encryption can be reduced from 688 to 340 per 128-bit block by using the proposed AES instructions. The execution unit for the AES instructions can be implemented efficiently with a single 2-Kbit table and four small multipliers. The capacity of the table has been reduced to 1/32, compared to that of a conventional fast software algorithm. The AES instructions enable embedded processors for low-cost network equipment to have cryptographic capability with minimal modification.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"123 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120880429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
FPGA implementation of high speed parallel architecture for block motion estimation FPGA实现高速并行结构的块运动估计
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363057
P. Rangarajan, G. Prashanth, P. Harish
{"title":"FPGA implementation of high speed parallel architecture for block motion estimation","authors":"P. Rangarajan, G. Prashanth, P. Harish","doi":"10.1109/SIPS.2004.1363057","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363057","url":null,"abstract":"The paper describes a high speed fully pipelined parallel architecture for the new three step search (NTSS) block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces an efficient solution for the realtime motion estimation required in video applications with a low memory-bandwidth requirement. This architecture can be used for various video applications from low bit-rate video to HDTV systems. This architecture was implemented using Verilog HDL with FPGA device Xilinx XCS2S300E as the target device, verifying its functionality.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120892843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications 基于子表达式共享的新型低功耗流水线FFT无线局域网应用
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363029
Wei Han, T. Arslan, A. Erdogan, M. Hasan
{"title":"Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications","authors":"Wei Han, T. Arslan, A. Erdogan, M. Hasan","doi":"10.1109/SIPS.2004.1363029","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363029","url":null,"abstract":"This paper proposes a novel low power multiplierless radix-4 single-path delay commutator (R4SDC) FFT processor architecture for wireless LAN (IEEE 802.11 standard) applications, where short FFT are utilised in the implementation of the physical layer. The multiplierless architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and low power butterfly architectures with this approach, the resulting power savings are around 19% and 35% for 64-point and 16-point radix-4 FFT respectively, as compared to a conventional FFT architecture based on non-Booth coded Wallace tree multiplier.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131769491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A novel forward-backward predictor based low-power DSP system 一种新型的基于前向向后预测器的低功耗DSP系统
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363072
B. Shim, Ming Zhang, N. Shanbhag
{"title":"A novel forward-backward predictor based low-power DSP system","authors":"B. Shim, Ming Zhang, N. Shanbhag","doi":"10.1109/SIPS.2004.1363072","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363072","url":null,"abstract":"In this paper, we present an algorithmic noise tolerance (ANT) technique for low-power digital signal processing systems. The proposed technique employs a low-complexity forward-backward predictor to correct errors in a main DSP (MDSP) block due to voltage overscaling, which is an ultra low-voltage operating condition. For a frequency selective FIR filtering, it is shown that the proposed technique achieves up to 43% power savings over an optimally voltage scaled MDSP with a 5% area overhead.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the complexity and performance of strategies for symbol detection in multi-antenna wireless LAN 多天线无线局域网中符号检测策略的复杂性和性能研究
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363021
J. Penketh, M. Collados
{"title":"On the complexity and performance of strategies for symbol detection in multi-antenna wireless LAN","authors":"J. Penketh, M. Collados","doi":"10.1109/SIPS.2004.1363021","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363021","url":null,"abstract":"This paper discusses the symbol detection complexity of several orthogonal frequency division multiplexing wireless communication schemes using multiple-input multiple-output channels. We investigate spatial diversity (SD) and spatial multiplexing (SM) architectures. For the SD case we discuss an efficient example of space-time block coding, namely the Alamouti scheme. For the SM case we examine linear filtering, using both the zero-forcing and minimum mean squared error design criteria, and also the nonlinear maximum likelihood detection method. A comparison of the packet error rate performance of the various systems is then provided, followed by a thorough analysis of implementational complexity.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127353508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packet transmission policies for battery operated communication systems 电池供电通信系统的分组传输策略
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363027
Ye Li, C. Chakrabarti
{"title":"Packet transmission policies for battery operated communication systems","authors":"Ye Li, C. Chakrabarti","doi":"10.1109/SIPS.2004.1363027","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363027","url":null,"abstract":"In this paper, we address the problem of designing battery-friendly packet transmission policies for wireless data transmission. Our objective is to maximize the lifetime of battery for wireless devices subject to certain delay constraints. We present three packet transmission schemes and evaluate them with respect to battery performance. The first scheme based on combining multiple packets, utilizes the battery charge recovery due to long idle periods. The second scheme based on a modified version of lazy packet scheduling, draws lower current and is battery efficient. The third scheme which is based on a combination of the above two schemes, has superior battery performance at the expense of larger average packet delay. All three schemes were simulated for a wireless communication framework with Internet traffic, and the results validated.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125848894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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