High-performance adaptive GPS attitude determination VLSI architecture

Abstract

The paper presents an adaptive VLSI hardware architecture for an attitude determination system (ADS), which is based on Global Positioning System (GPS) measurements. The system composes the digital core of a GPS receiver, which manipulates the input data in order to resolve the attitude of a vehicle. The adaptation of this architecture is achieved by using a fine-grained parallel genetic algorithm (PGA) that is employed to compute more efficiently the attitude determination algorithm in terms of speed performance. The PGA consists of 64 processing elements (PEs), which are connected in the formation of an 8/spl times/8 array. Moreover, the hardware block that computes the fitness function of the PGA employs coordinate rotation digital computer (CORDIC) algorithms in order to increase the throughput rate of the ADS further.