FPGA implementation of high speed parallel architecture for block motion estimation

The paper describes a high speed fully pipelined parallel architecture for the new three step search (NTSS) block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing external memory accesses are also developed. The proposed architecture produces an efficient solution for the realtime motion estimation required in video applications with a low memory-bandwidth requirement. This architecture can be used for various video applications from low bit-rate video to HDTV systems. This architecture was implemented using Verilog HDL with FPGA device Xilinx XCS2S300E as the target device, verifying its functionality.