{"title":"Self-Monitoring, Self-Healing Biomorphic Sensor Technology","authors":"A. Richardson, D. Cheneler","doi":"10.1109/IOLTS.2019.8854453","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854453","url":null,"abstract":"The deployment of autonomous sensors within electronic systems for both existing and emerging markets requires an increase in the reliability, security and dependability of the associated data generated. The availability of intelligent sensors that can self-adapt and ultimately self-heal would be a key step towards this objective. This paper presents ideas associated with the utilisation of sensor self-test principles and software algorithms able to generate sensor prognostics and drive adaptation, compensation and self-healing functions. Major initiatives supported both within Europe and further afield to migrate processing power to the “Edge”, deploy 5G technologies and integrate Artificial Intelligence across the system hierarchy provide technological platforms to deliver many of these concepts. An example associated with simple printed electrodes targeting corrosion detection and potentially the detection of hydrogen is presented in the context of a step towards full biomorphic capability.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129701633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Khandelwal, Anu Bala, Vishal Gupta, V. Gupta, M. Ottavi, E. Martinelli, A. Jabir
{"title":"Fault Modeling and Simulation of Memristor based Gas Sensors","authors":"S. Khandelwal, Anu Bala, Vishal Gupta, V. Gupta, M. Ottavi, E. Martinelli, A. Jabir","doi":"10.1109/IOLTS.2019.8854459","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854459","url":null,"abstract":"Memristors are an attractive option for use in future architectures due to their non-volatility, high density and low power operation. Gas sensing is one of the proposed application of memristive devices. In spite of these advantages, memristors are susceptible to defect densities due to the nondeterministic nature of nano-scale fabrication. In this paper, a novel spice memristor model incorporating fault models that emulates the gas sensing behaviour with/without faults is developed for simulation and integration with design automation tools. Our simulation results show that the proposed non-linear model detects the presence of the oxidising/reducing gas and analyses the defects/faults affecting the functionality of the sensor.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116635727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IOLTS 2019 Technical Papers","authors":"","doi":"10.1109/iolts.2019.8854408","DOIUrl":"https://doi.org/10.1109/iolts.2019.8854408","url":null,"abstract":"","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126146250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Constantinos Xanthopoulos, Arnold Neckermann, Paulus List, Klaus-Peter Tschernay, Peter Sarson, Y. Makris
{"title":"Automated Die Inking through On-line Machine Learning","authors":"Constantinos Xanthopoulos, Arnold Neckermann, Paulus List, Klaus-Peter Tschernay, Peter Sarson, Y. Makris","doi":"10.1109/IOLTS.2019.8854373","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854373","url":null,"abstract":"Ensuring high reliability in modern integrated circuits (ICs) requires the employment of several die screening methodologies. One such technique, commonly referred to as die inking, aims to discard devices that are likely to fail, based on their proximity to known failed devices on the wafer. Die inking is traditionally performed manually by visually inspecting each manufactured wafer and thus it is very time-consuming. Recently, machine learning has been used to automate and speed-up the inking process. In this work, we employ on-line machine learning to address the practicability limitations of the current state-of the-art automated inking approach. Effectiveness is demonstrated on an industrial dataset of manually inked wafers.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mhamdi, A. Virazel, P. Girard, A. Bosio, E. Auvray, E. Faehn, A. Ladhar
{"title":"Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip","authors":"S. Mhamdi, A. Virazel, P. Girard, A. Bosio, E. Auvray, E. Faehn, A. Ladhar","doi":"10.1109/IOLTS.2019.8854388","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854388","url":null,"abstract":"In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today’s intra-cell diagnosis tools based on effect-cause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115519905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, K. Chakrabarty, R. Karri
{"title":"Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?","authors":"Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, K. Chakrabarty, R. Karri","doi":"10.1109/IOLTS.2019.8854393","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854393","url":null,"abstract":"Researchers develop bioassays by rigorously experimenting in the lab. This involves significant fiscal and skilled person-hour investment. A competitor can reverse engineer a bioassay implementation by imaging or taking a video of a biochip when in use. Thus, there is a need to protect the intellectual property (IP) rights of the bioassay developer. We introduce a novel 3D multilayer-based obfuscation to protect a biochip against reverse engineering.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Nair, R. Bishnoi, M. Tahoori, H. Grigoryan, Grigor Tshagharyan
{"title":"Variation-aware Fault Modeling and Test Generation for STT-MRAM","authors":"S. Nair, R. Bishnoi, M. Tahoori, H. Grigoryan, Grigor Tshagharyan","doi":"10.1109/IOLTS.2019.8854376","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854376","url":null,"abstract":"Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) offers high density, non-volatility, scalability, high endurance and CMOS compatibility, making it a promising non-volatile memory (NVM) technology. However, due to the unique magnetic fabrication processes, different bit-cell architecture and periphery circuitry, they are susceptible to different manufacturing defects and faults compared to conventional CMOS-based memories. In this paper, a detailed variation-aware defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129589211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mitsunori Ebara, Kodai Yamada, J. Furuta, Kazutoshi Kobayashi
{"title":"Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process","authors":"Mitsunori Ebara, Kodai Yamada, J. Furuta, Kazutoshi Kobayashi","doi":"10.1109/IOLTS.2019.8854436","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854436","url":null,"abstract":"We examined radiation hardness of a stacked transmission-gate flip flop and a stacked tristate-inverter flip flop, which are called STACKEDTGFF and STACKEDTIFF respectively. Stacked flip flops fabricated in FDSOI are stronger against soft errors than in bulk because all transistor channels are isolated by a BOX layer. We evaluated soft-error tolerance by neutron and heavy-ion irradiation. STACKEDTIFF is faster than STACKEDTGFF because of the difference of the number of gates along the data path. Those FFs did not flip by neutrons and the normal incidence of heavy ions with LET of less than 40 MeV-cm2mg. They are stronger against soft errors than a standard TGFF by two order of magnitude. We also investigated incident angle dependence of those FFs by heavy ions.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128368023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient Methodology for ISO26262 Functional Safety Verification","authors":"F. A. D. Silva, A. Bagbaba, S. Hamdioui, C. Sauer","doi":"10.1109/IOLTS.2019.8854449","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854449","url":null,"abstract":"Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Gizopoulos, G. Papadimitriou, Athanasios Chatzidimitriou, V. Reddi, Behzad Salami, O. Unsal, A. Cristal, Jingwen Leng
{"title":"Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies","authors":"D. Gizopoulos, G. Papadimitriou, Athanasios Chatzidimitriou, V. Reddi, Behzad Salami, O. Unsal, A. Cristal, Jingwen Leng","doi":"10.1109/IOLTS.2019.8854386","DOIUrl":"https://doi.org/10.1109/IOLTS.2019.8854386","url":null,"abstract":"Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. Voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.","PeriodicalId":383056,"journal":{"name":"2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132151465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}