Variation-aware Fault Modeling and Test Generation for STT-MRAM

Abstract

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) offers high density, non-volatility, scalability, high endurance and CMOS compatibility, making it a promising non-volatile memory (NVM) technology. However, due to the unique magnetic fabrication processes, different bit-cell architecture and periphery circuitry, they are susceptible to different manufacturing defects and faults compared to conventional CMOS-based memories. In this paper, a detailed variation-aware defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.