{"title":"Computing and Communication in the New Millennium","authors":"A. Saini","doi":"10.1109/VLSID.2000.10012","DOIUrl":"https://doi.org/10.1109/VLSID.2000.10012","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122024464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EDA-The Next Generation","authors":"Ajoy K. Bose","doi":"10.1109/VLSID.2000.10014","DOIUrl":"https://doi.org/10.1109/VLSID.2000.10014","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IP Reuse in System on a Chip Design","authors":"R. Camposano, W. Savage, J. Chilton","doi":"10.1109/VLSID.2000.10016","DOIUrl":"https://doi.org/10.1109/VLSID.2000.10016","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Surviving the SOC Revolution: The Platform Approach to SOC Design","authors":"G. Martin","doi":"10.1109/VLSID.2000.10015","DOIUrl":"https://doi.org/10.1109/VLSID.2000.10015","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CAD Techniques for Embedded System Design","authors":"S. Devadas, S. Malik, J. Monteiro, L. Lavagno","doi":"10.1109/VLSID.1999.10016","DOIUrl":"https://doi.org/10.1109/VLSID.1999.10016","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Vittal, L. Chen, M. Marek-Sadowska, Kai-Ping Wang, Sherry Yang
{"title":"Modeling Crosstalk in Resistive VLSI Interconnections","authors":"A. Vittal, L. Chen, M. Marek-Sadowska, Kai-Ping Wang, Sherry Yang","doi":"10.1109/ICVD.1999.745200","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745200","url":null,"abstract":"We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128202696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low Power Design Methodologies for Systems-on-Chips","authors":"K. Roy, A. Raghunathan, S. Dey","doi":"10.1109/VLSID.1999.10012","DOIUrl":"https://doi.org/10.1109/VLSID.1999.10012","url":null,"abstract":"Advances in semiconductor technologies, and the aggressive time-to-market, performance, and cost requirements have led to a paradigm shift in electronic system design, with the evolution of system-level-integration allowing an entire system to be integrated on a single chip. At the same time, the applications which stand to benefit most from the use of embedded system-on-chips, like portable telecommunication products, have increasingly critical needs for low power consumption. Modern system-on-chips (SOCs) are characterized by the presence of heterogeneous components: digital components like CPUs, DSPs, and multimedia cores, network interfaces, analog components like RF transceivers and ADC/DAC cores, high-speed custom-designed blocks, as well as asynchronous interfaces. The heterogeneity of system-on-chips, along with the effects of the use of deep submicron technologies, makes design of efficient low-power SOCs challenging. This tutorial addresses the challenges, new methodologies proposed, and current industrial practices in the design and analysis of low-power deep-submicron system-on-chips.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127441777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Keynote Address: The Networked Society - Enabled by DSP Solutions","authors":"P. Chatterjee","doi":"10.1109/VLSID.1998.10002","DOIUrl":"https://doi.org/10.1109/VLSID.1998.10002","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128312269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel: Challenges for Future Systems on a Chip","authors":"R. Jain","doi":"10.1109/VLSID.1998.10001","DOIUrl":"https://doi.org/10.1109/VLSID.1998.10001","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127598134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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