{"title":"Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies","authors":"R. Puri, T. Karnik, R. Joshi","doi":"10.1109/VLSID.2006.156","DOIUrl":"https://doi.org/10.1109/VLSID.2006.156","url":null,"abstract":"Summary form only for tutorial. This tutorial discusses design challenges of scaled CMOS circuits in sub-90nm technologies and the design methodologies required to design them in order to produce robust designs with desired power performance trade-off. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines. On the technology front, the question arises whether we can continue along the traditional CMOS scaling path - reduce effective oxide thickness, improve channel mobility, and minimize parasitics. On the design front, researchers are exploring various circuit design techniques to deal with process variation, leakage and soft errors.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120853332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Embedded Systems with Novel Applications","authors":"R. Lacovara, D. Vaman","doi":"10.1109/VLSID.2006.66","DOIUrl":"https://doi.org/10.1109/VLSID.2006.66","url":null,"abstract":"Summary form only for tutorial. The tutorial introduces the need for restructuring the embedded systems designs with focus on new time critical network centric applications, where full duplex control function plays a vital role over typical interfaces such as LANs, DSLs and serial & parallel ports. Time critical applications are extremely sensitive to random variations of processing times, scheduling information exchanges and clock jitters. These variations produce excessive random delays that are highly problematic for time critical applications. Currently implemented interfaces such as bus architectures and local area network interfaces produce excessive random delays both in expected value and its standard deviation. The embedded systems design needs to take into account the problems with respect to enhancing the existing interfaces as well as developing new interfaces.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122133787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-Power Design Strategies for Mobile Computing","authors":"A. Prasad, Jacob Mathews, N. Naganathan","doi":"10.1109/VLSID.2006.114","DOIUrl":"https://doi.org/10.1109/VLSID.2006.114","url":null,"abstract":"Summary form only for tutorial. The advent of nanometer design process has enabled the integration of multi-million gates with a variety of functionality as a system-on-chip (SoC). The demand for high levels of integration in SoCs are fueled by a strong demand in consumer oriented products for hand held computing, multimedia and other communication products. For these products, power budget is a very critical factor deciding the battery life, size and weight of the portable devices. Designers need to use energy reduction techniques to support as many design features and functions and still keep within the system power budget. The tutorial presents a comprehensive introduction to low power design techniques, and challenges in various facets of the design process. We present an in-depth introduction to concepts with a holistic view to overcome the various challenges and present strategies with a practical approach to the key issues in the design of low power solutions. All the techniques are discussed with practical examples.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130985756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Challenges for High Performance Nano-Technology","authors":"Goutam Debnath, P. J. Thadikaran","doi":"10.1109/VLSID.2006.64","DOIUrl":"https://doi.org/10.1109/VLSID.2006.64","url":null,"abstract":"Summary form only for tutorial. This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nanotechnology. The focus is on design challenges that are experienced in microprocessor designs. It captures the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification. It describes the requirements to meet power, timing, physical dimension and process portability goals with nanotechnology. It also addresses the pre and post silicon verification difficulties that have a direct impact on taking the product to market.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129121659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Technological and Geographical Migration of the Semiconductor Industry","authors":"Jackson Hu","doi":"10.1109/VLSID.2006.161","DOIUrl":"https://doi.org/10.1109/VLSID.2006.161","url":null,"abstract":"The first transistor was invented in late 1947. In less than sixty years, this innovation has led to the creation of global semiconductor and IT industries which have had a tremendous impact on human life. In his speech, Dr. Jackson Hu first reviews the technology migration from discrete transistor to SoC (system on chip). He then addresses how the semiconductor industry has migrated from the USA to the rest of the world, and discuss the implications to emerging regions such as India and China.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126239371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"65nm Omnibudsman","authors":"T. Vucurevich","doi":"10.1109/ICVD.2005.5","DOIUrl":"https://doi.org/10.1109/ICVD.2005.5","url":null,"abstract":"Summary form only given. Just as the semiconductor industry has begun to ship production products at 90nm we find ourselves starting \"pipe cleaner\" designs at 65nm. Each process generation provides both opportunities and challenges to design teams and the 65nm node is no exception. This paper provides a short overview of the challenges of designing at 65nm with special emphasis on the relationship of the design process to the manufacturing process and what is changing in the way that design tools keep complexity at bay in a world where power density and process variability threaten to drive us off of Moore's now famous law.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Moore's Law is Unconstitutional","authors":"W. Rhines","doi":"10.1109/ICVD.2005.121","DOIUrl":"https://doi.org/10.1109/ICVD.2005.121","url":null,"abstract":"Moore's law is the empirical observation that component density and performance of integrated circuits - approximately doubles every eighteen months. It is not a 'law' in the sense that basic principals of physics and thermodynamics constitute the rules of nature. But there is a 'law' that serves as the basis for Moore's law; it is the general principle that governs learning curves, i.e. that efficiencies improve a fixed percentage with increases in the total accumulated volume of production, when analyzed on a logarithmic scale. Analyzing current trends in integrated circuit technology reveals the potential left to achieve performance, reliability and cost improvements via the traditional means of shrinking design rules and increasing die and wafer size. It also suggests where nontraditional innovation is likely to have its greatest impact. This talk explores these projections for future technology and suggest where the discontinuities are most likely to occur.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124304535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ESL - The Next Leadership Opportunity for India?","authors":"A. Naumann","doi":"10.1109/ICVD.2005.92","DOIUrl":"https://doi.org/10.1109/ICVD.2005.92","url":null,"abstract":"Summary form only given. This paper lectures on the increasingly critical role played by electronic system level (ESL) design tools in the development of the complex system-on-chip (SoC) devices that are now the indispensable engines of advanced consumer and communications products. Drawing upon his experience in managing CoWare, which has world-class software development resources in India, the author argues that ESL tool development expertise can be an effective differentiator for Indian software engineering. This paper discusses the growing impact of SoC technology on the global electronics market, and the factors driving it. In particular, contrary to the conventional wisdom, the design cost per gate continues to fall - because rising mask costs are more than offset by the massive increase in the number of gates per chip. This increase in gate capacity presents SoC designers not only with a significant market opportunity, but also with a serious design challenge - how to integrate so much functionality into one chip without the multiple re-spins that destroy a product's time to market and bury its design budget. Also discussed is the ESL design methodology, and it is argued that the adoption of such a methodology is a pre-requisite for meeting this SoC design challenge. This paper argues that Indian engineers - with their proven expertise in software modelling and development - can occupy a pole position in this new industrial revolution.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI Design Challenges for Gigascale Integration","authors":"S. Borkar","doi":"10.1109/ICVD.2005.171","DOIUrl":"https://doi.org/10.1109/ICVD.2005.171","url":null,"abstract":"VLSI system performance increased by five orders of magnitude in the last three decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue, providing integration capacity of billions of transistors; however, power and energy consumption will be the barriers. Performance at any cost will not be an option in the future; VLSI systems will have to emphasize performance delivered in a given power envelope, with complexity limited by energy efficiency. This paper discusses potential solutions in process technology, circuits, and microarchitectures to exploit future gigascale integration capacity. The system on a chip (SOC) concept will help integrate diverse functional blocks, providing valued performance. The paper concludes with recommendations to the VLSI system designers on how to exploit these emerging paradigms.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130376047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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