{"title":"T5: Low-Power Design","authors":"K. Roy, R. Roy, R. Harjani, K. Murthy","doi":"10.1109/VLSID.1997.10015","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10015","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124051882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"T4: Verification","authors":"R. Raina, J. Abraham, A. K. Pujari","doi":"10.1109/VLSID.1997.10010","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10010","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114697655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Register Transfer Level Synthesis: From Theory to Practice","authors":"K. Keutzer, S. Malik","doi":"10.1109/VLSID.1996.10009","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10009","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Practical Test and DFT for Next Generation VLSI","authors":"J. Abraham, G. Ganapathy","doi":"10.1109/VLSID.1996.10011","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10011","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reasoning about the Trends and Challenges of Engineering Design Automation","authors":"A. Sangiovanni-Vincentelli","doi":"10.1109/VLSID.2007.135","DOIUrl":"https://doi.org/10.1109/VLSID.2007.135","url":null,"abstract":"In this paper, the author discusses the raising level of abstraction when designing chips and dealing with electronics system design and in particular, embedded system design. In this framework, the term system-level design for an integrated circuit relates to any level of abstraction that is \"above\" RTL and the term embedded systems refers to the electronic components of a wide variety of personal or societal devices, e.g., a mechanical system such as an automobile, a train, a plane, an electrical system such as an electrical motor or generator, a chemical system such as a distillation plant, a health-care equipment such as a pace-maker","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity","authors":"M. G. Mohammad, L. Terkawi, M. Albasman","doi":"10.1109/VLSID.2006.26","DOIUrl":"https://doi.org/10.1109/VLSID.2006.26","url":null,"abstract":"With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as single-event-upset (SEU), is a growing concern in logic circuits. Accurate understanding and estimation of single-event-upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to study the effect of inputs, circuit structure and delay on single-event-upset sensitivity of nodes in logic circuits as a single joint probability distribution function (PDF). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint PDF which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}