VLSI design (Print)最新文献

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T5: Low-Power Design T5:低功耗设计
VLSI design (Print) Pub Date : 1997-01-04 DOI: 10.1109/VLSID.1997.10015
K. Roy, R. Roy, R. Harjani, K. Murthy
{"title":"T5: Low-Power Design","authors":"K. Roy, R. Roy, R. Harjani, K. Murthy","doi":"10.1109/VLSID.1997.10015","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10015","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124051882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
T2: HW-SW Codesign T2: HW-SW协同设计
VLSI design (Print) Pub Date : 1997-01-04 DOI: 10.1109/VLSID.1997.10011
P. Subrahmanyam, R. Gupta, B. Rao
{"title":"T2: HW-SW Codesign","authors":"P. Subrahmanyam, R. Gupta, B. Rao","doi":"10.1109/VLSID.1997.10011","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10011","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129627151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
T4: Verification T4:验证
VLSI design (Print) Pub Date : 1997-01-04 DOI: 10.1109/VLSID.1997.10010
R. Raina, J. Abraham, A. K. Pujari
{"title":"T4: Verification","authors":"R. Raina, J. Abraham, A. K. Pujari","doi":"10.1109/VLSID.1997.10010","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10010","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114697655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
T3: Physical Design T3:物理设计
VLSI design (Print) Pub Date : 1997-01-04 DOI: 10.1109/VLSID.1997.10014
D. Mehta, N. Sherwani, A. Bariya
{"title":"T3: Physical Design","authors":"D. Mehta, N. Sherwani, A. Bariya","doi":"10.1109/VLSID.1997.10014","DOIUrl":"https://doi.org/10.1109/VLSID.1997.10014","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Register Transfer Level Synthesis: From Theory to Practice 语域迁移层综合:从理论到实践
VLSI design (Print) Pub Date : 1996-01-03 DOI: 10.1109/VLSID.1996.10009
K. Keutzer, S. Malik
{"title":"Register Transfer Level Synthesis: From Theory to Practice","authors":"K. Keutzer, S. Malik","doi":"10.1109/VLSID.1996.10009","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10009","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Practical Test and DFT for Next Generation VLSI 下一代VLSI的实际测试和DFT
VLSI design (Print) Pub Date : 1996-01-03 DOI: 10.1109/VLSID.1996.10011
J. Abraham, G. Ganapathy
{"title":"Practical Test and DFT for Next Generation VLSI","authors":"J. Abraham, G. Ganapathy","doi":"10.1109/VLSID.1996.10011","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10011","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Software Co-Design of Embedded Systems 嵌入式系统的软硬件协同设计
VLSI design (Print) Pub Date : 1996-01-03 DOI: 10.1109/VLSID.1996.10007
{"title":"Hardware Software Co-Design of Embedded Systems","authors":"","doi":"10.1109/VLSID.1996.10007","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10007","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mixed-Signal Design for Test 混合信号测试设计
VLSI design (Print) Pub Date : 1900-01-01 DOI: 10.1109/VLSID.1996.10015
B. Vinnakota, R. Harjani
{"title":"Mixed-Signal Design for Test","authors":"B. Vinnakota, R. Harjani","doi":"10.1109/VLSID.1996.10015","DOIUrl":"https://doi.org/10.1109/VLSID.1996.10015","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125348254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reasoning about the Trends and Challenges of Engineering Design Automation 工程设计自动化的趋势和挑战推理
VLSI design (Print) Pub Date : 1900-01-01 DOI: 10.1109/VLSID.2007.135
A. Sangiovanni-Vincentelli
{"title":"Reasoning about the Trends and Challenges of Engineering Design Automation","authors":"A. Sangiovanni-Vincentelli","doi":"10.1109/VLSID.2007.135","DOIUrl":"https://doi.org/10.1109/VLSID.2007.135","url":null,"abstract":"In this paper, the author discusses the raising level of abstraction when designing chips and dealing with electronics system design and in particular, embedded system design. In this framework, the term system-level design for an integrated circuit relates to any level of abstraction that is \"above\" RTL and the term embedded systems refers to the electronic components of a wide variety of personal or societal devices, e.g., a mechanical system such as an automobile, a train, a plane, an electrical system such as an electrical motor or generator, a chemical system such as a distillation plant, a health-care equipment such as a pace-maker","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity 单事件扰动敏感性的无刺激概率模型
VLSI design (Print) Pub Date : 1900-01-01 DOI: 10.1109/VLSID.2006.26
M. G. Mohammad, L. Terkawi, M. Albasman
{"title":"A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity","authors":"M. G. Mohammad, L. Terkawi, M. Albasman","doi":"10.1109/VLSID.2006.26","DOIUrl":"https://doi.org/10.1109/VLSID.2006.26","url":null,"abstract":"With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as single-event-upset (SEU), is a growing concern in logic circuits. Accurate understanding and estimation of single-event-upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to study the effect of inputs, circuit structure and delay on single-event-upset sensitivity of nodes in logic circuits as a single joint probability distribution function (PDF). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint PDF which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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