Low Power Design Methodologies for Systems-on-Chips

Abstract

Advances in semiconductor technologies, and the aggressive time-to-market, performance, and cost requirements have led to a paradigm shift in electronic system design, with the evolution of system-level-integration allowing an entire system to be integrated on a single chip. At the same time, the applications which stand to benefit most from the use of embedded system-on-chips, like portable telecommunication products, have increasingly critical needs for low power consumption. Modern system-on-chips (SOCs) are characterized by the presence of heterogeneous components: digital components like CPUs, DSPs, and multimedia cores, network interfaces, analog components like RF transceivers and ADC/DAC cores, high-speed custom-designed blocks, as well as asynchronous interfaces. The heterogeneity of system-on-chips, along with the effects of the use of deep submicron technologies, makes design of efficient low-power SOCs challenging. This tutorial addresses the challenges, new methodologies proposed, and current industrial practices in the design and analysis of low-power deep-submicron system-on-chips.