2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献_第7页

Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD 分析了静电放电产生的栅极电场和磁场对地栅和浮栅功率晶体管静电放电差异的影响

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915710

Jian-Hsing Lee, K. Nidhi, Tingyou Lin, Hsueh-Chun Liao, Scott Lee, M. Ker

{"title":"Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD","authors":"Jian-Hsing Lee, K. Nidhi, Tingyou Lin, Hsueh-Chun Liao, Scott Lee, M. Ker","doi":"10.1109/IPFA55383.2022.9915710","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915710","url":null,"abstract":"The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Abbreviated tomography techniques for quick correction of slides in 3-Dimensional NAND Flash architectures 三维NAND闪存结构中载玻片快速校正的简化断层扫描技术

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915708

Hee-Beom Lee, M. Ishimaru, J. Mcphillips, R. Alvis, Timothy A. Johnson, C. H. Kang, Inchang Choi, Youngjin Cho, Kiju Choi

{"title":"Abbreviated tomography techniques for quick correction of slides in 3-Dimensional NAND Flash architectures","authors":"Hee-Beom Lee, M. Ishimaru, J. Mcphillips, R. Alvis, Timothy A. Johnson, C. H. Kang, Inchang Choi, Youngjin Cho, Kiju Choi","doi":"10.1109/IPFA55383.2022.9915708","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915708","url":null,"abstract":"A high stack structure is being developed to increase the 3D NAND Flash storage capacity. However, problems such as bowing, incomplete etching, and twisting occur during the channel hole etching process. For the analysis of these process problems, cross-sectional analysis of devices with high stacks is essential.However, it is difficult to uniformly measure the top and bottom layers of the source line contact and V-NAND string area. Therefore, distortion occurs through cross section analysis. The reasons include the focused ion beam incident beam angle relative to the sample coordinate system, beam current profile, and differential milling.The listed physical parameters can be adjusted in a way to obtain distortion-improved, uniform, and perpendicular image data; however, this time-consuming task is a hindrance when trying to increase the reliability of the analysis.In order to address this problem, we propose an efficient processing technique, abbreviated tomography, which is an efficient data reconstruction method.In this study, 248 images were prepared to set up the tomography algorithm data set. The data was reconstructed in a significantly reduced time using the abbreviated tomography technique. Although it took an average of 5 h to obtain 248 new 2D images, we were able to reconstruct the data in 4 min using the abbreviated tomography technique. This abbreviated tomography algorithm can be used as an efficient reconstruction tool for studying structure at the most basic level.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SiC/SiO2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain SiC/SiO2界面陷阱对SiC mosfet偏漏栅电容的影响

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915748

I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, A. Castellazzi, S. Daliento

引用次数: 4

Characterization of Oxide Layers on AlGaN Based DUV LEDs by TEM/STEM Analysis 用TEM/STEM分析表征AlGaN基DUV led氧化层

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915764

J. Bow, Jay Wang, W. Lai, Tien Y. Wang, Syuan-Yu Sie, Sheng-Po Chang, C. Kuo, J. Sheu

引用次数: 0

A novel method combining laser ablation and chemical etch to expose packaged silicon backside for electrical fault isolation 采用激光烧蚀和化学蚀刻相结合的方法暴露封装硅背面，实现电气故障隔离

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915784

S. L. Ting, P. K. Tan, M. Seungje, J. C. Alag, Yanlin Pan, Hnin Hnin, T. T. Yu, K. Kang, A. Quah, C. Chen

引用次数: 0

Inspection methodologies and machine-learning approaches for defectivity data in semiconductor industry for automotive applications: case study for field-failure prevention 用于汽车应用的半导体工业缺陷数据的检测方法和机器学习方法:现场故障预防的案例研究

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915769

C. Bergès, J. Bird, M. Shroff, Edwin Lumanauw, Sreerag Raghunathan, Chris Smith

{"title":"Inspection methodologies and machine-learning approaches for defectivity data in semiconductor industry for automotive applications: case study for field-failure prevention","authors":"C. Bergès, J. Bird, M. Shroff, Edwin Lumanauw, Sreerag Raghunathan, Chris Smith","doi":"10.1109/IPFA55383.2022.9915769","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915769","url":null,"abstract":"Big-data infrastructure and environment enable the ability to connect and store data to develop and deploy machine-learning activities and analysis in various industries. Equipment manufacturers are implementing new artificial-intelligence capabilities on their tool platforms, thus pushing manufacturers themselves to use data provided by these new functionalities and to link them with other data from their processes. Then, the manufacturer who uses this new artificial-intelligence data is seeking to connect them to some other of internal data, such as the electrical test results per die, in a new type of analysis, with the purpose to improve the screening offered by the electrical test, and thus to increase overall quality. This paper reports new capabilities in automated optical inspection, implemented in automotive-semiconductor manufacturing, which predict a probability of failure per die, computed by the inspection equipment from the features of the observed defects, and presents some significant results in the case of a product implemented in automotive RADAR products.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124213981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Characterization analysis of aluminum pad discoloration and ions contamination monitor of wafer storage environment 铝垫变色特性分析及晶圆储存环境离子污染监测

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915755

F. Su, Ray Tu, W. Hsieh, Henry Lin, Vincent Chen, Irene Ou, Y. Lou

引用次数: 0

Studies of Passivation (Si3N4/SiO2) Qualification Method in Wafer Fabrication 硅片制造中钝化(Si3N4/SiO2)鉴定方法的研究

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915786

Younan Hua, Jin Liao, Binhai Liu, Lei Zhu, Xiaomin Li

{"title":"Studies of Passivation (Si3N4/SiO2) Qualification Method in Wafer Fabrication","authors":"Younan Hua, Jin Liao, Binhai Liu, Lei Zhu, Xiaomin Li","doi":"10.1109/IPFA55383.2022.9915786","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915786","url":null,"abstract":"In wafer fabrication, silicon nitride (Si3N4) and silicon oxide (SiO2) layers are widely used as passivation layer to protect the Al metal underneath from corrosion. To qualify the passivation layers, the traditional chemical recipe PAE (H3PO4 + HNO3) is used to conduct passivation pinhole test. If pinholes or cracks are present in the passivation layer of Si3N4/SiO2, the sample immersion in the test solution duration will allow HNO3 acid to chemically react with the Al layer underneath. Therefore, a black colored pinhole-like defect will be observed during optical inspection after the pinhole test. In this situation, the wafer sample fails the pinhole test and is not qualified.If there is no pinhole or crack in the passivation layers of Si3N4/SiO2, after the sample immersion in the testing solution time, HNO3 acid cannot chemically react with the underneath aluminum layer. The black pinhole-like defect during optical inspection is unable to be detected, and the wafer sample passes the pinhole test. However, this traditional method has its limitation. If the pinholes or cracks do not completely penetrate the entire passivation layer, in this case HNO3 acid cannot flow into the pinholes or cracks and could not chemically react with the underlying aluminum. As a result, those pinholes or cracks could not be detected.In this study, we proposed a new test method to replace the traditional pinhole test method by using fluorescent dye method. We have developed a fluorescence microscopy method which can be applied to qualify the passivation layer. Using this new method, we could detect pinholes/cracks in passivation layer in wafer fabrication which had totally or partially penetrate the entire passivation (Si3N4/SiO2) layer. The smallest microcrack size currently detected can reach 72nm. All micro-pinhole defects can be detected by fluorescence microscopy method, which can detect not only full perforation defects, but also those partially perforated defects.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132018817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Failures of Ag Wire Bonding ICs in Real-world Applications 银线键合集成电路在实际应用中的故障

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915707

Xuanlong Chen, Xiaping Xie, Min Wang, Yongjia Ruan, Tianhan Liu, Lin Shi

引用次数: 0

Statistical Study of Electromigration in Gold Interconnects 金互连中电迁移的统计研究

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2022-07-18 DOI: 10.1109/IPFA55383.2022.9915762

H. Ceric, R. L. de Orio, S. Selberherr

引用次数: 0