发布求助
文献互助 智能选刊 最新文献

ESSCIRC 76: 2nd European Solid State Circuits Conference最新文献

筛选
英文 中文
2 GHz Logic based on a 5 GHz fT Process 基于5ghz fT工艺的2ghz逻辑
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469076
M. Kitchin, P. S. Walsh, P. Ward
{"title":"2 GHz Logic based on a 5 GHz fT Process","authors":"M. Kitchin, P. S. Walsh, P. Ward","doi":"10.1109/ESSCIRC.1976.5469076","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469076","url":null,"abstract":"The first optimised designs for the high speed variant of Plessey's Bipolar Process III have been evaluated. Process features will be followed by performance details for a 500 pSec ECL gate, a ring oscillator and divider circuits.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121213405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Optical Character Recognition Device 光学字符识别装置
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469239
W. D. Ryan, D. H. Campbell, D. H. Campbell
{"title":"Optical Character Recognition Device","authors":"W. D. Ryan, D. H. Campbell, D. H. Campbell","doi":"10.1109/ESSCIRC.1976.5469239","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469239","url":null,"abstract":"This Optical Character Recognition Device comprises a 7 × 5 photo diode matrix connected via polysilicon gates so that an adaptive linear discriminant function is obtained at the output. Practical results will be presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
1024-Bit Fully Decoded MNOS Non-Volatile Memory 1024位全解码MNOS非易失性存储器
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/esscirc.1976.5469232
D. Bostock
{"title":"1024-Bit Fully Decoded MNOS Non-Volatile Memory","authors":"D. Bostock","doi":"10.1109/esscirc.1976.5469232","DOIUrl":"https://doi.org/10.1109/esscirc.1976.5469232","url":null,"abstract":"A 1024-bit fully decoded MNOS memory is described which is fabricated using silicon-on-sapphire technology to provide the required isolation between the MNOS memory array and the decoding circuitry.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127029189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit Implications of the P.S.D.-MOST Process psd - most过程的电路含义
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469086
Ir. L. Spaanenburg
{"title":"Circuit Implications of the P.S.D.-MOST Process","authors":"Ir. L. Spaanenburg","doi":"10.1109/ESSCIRC.1976.5469086","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469086","url":null,"abstract":"The P.S.D.-MOST process will be compared to the polysilicon-gate process. It is shown, that P.S.D. circuitry occupy slightly less area at a higher switching speed.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134236218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Schottky I2L (Substrate Fed Logic) - An Optimum Form of I2L 肖特基I2L(衬底馈入逻辑)- I2L的一种最佳形式
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469090
P. S. Walsh, G. Sumerling
{"title":"Schottky I2L (Substrate Fed Logic) - An Optimum Form of I2L","authors":"P. S. Walsh, G. Sumerling","doi":"10.1109/ESSCIRC.1976.5469090","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469090","url":null,"abstract":"An advanced form of I2L, Schottky I2L, has been designed. Minimum delays ~ 10 ns at 50 ¿W and very high packing densities are attainable. Initial yield evaluation suggests that 1000 gate structures should be readily achieved.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
From Where to Where in Logic Arrays 从哪里到哪里的逻辑阵列
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/esscirc.1976.5469256
H. Fleisher
{"title":"From Where to Where in Logic Arrays","authors":"H. Fleisher","doi":"10.1109/esscirc.1976.5469256","DOIUrl":"https://doi.org/10.1109/esscirc.1976.5469256","url":null,"abstract":"","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Travelling Wave Dividers Up to 1.4 GHz 高达1.4 GHz的行波分频器
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469077
D. Grenier, D. Kasperkovitz
{"title":"Travelling Wave Dividers Up to 1.4 GHz","authors":"D. Grenier, D. Kasperkovitz","doi":"10.1109/ESSCIRC.1976.5469077","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469077","url":null,"abstract":"A new type of frequency divider in a subnanosecond process is described. The maximum toggle frequency is more than 1.4GHz. Driven with sinusoidal input voltage, the circuit requires an amplitude of less than 50mVrms between 150MHz and 1.1GHz.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132879026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaAs Integrated Circuits for High Speed Logic 用于高速逻辑的GaAs集成电路
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469078
D. Boccon-Gibod, G. Durand
{"title":"GaAs Integrated Circuits for High Speed Logic","authors":"D. Boccon-Gibod, G. Durand","doi":"10.1109/ESSCIRC.1976.5469078","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469078","url":null,"abstract":"An evaluation of the performances of logical gates with GaAs MESFET's in the Gb/s range is made on the basis of computational and experimental results.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130967973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a Very Large Reconfigurable Memory 超大可重构存储器的设计
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469236
Ayache Jean-Michel
{"title":"Design of a Very Large Reconfigurable Memory","authors":"Ayache Jean-Michel","doi":"10.1109/ESSCIRC.1976.5469236","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469236","url":null,"abstract":"We discuss in this paper, the design of a very large scale integrated memory. This memory is composed of partly faulty LSI chips and reconfiguration circuitry masking the faulty bits. Different reconfiguration policies are given leading to memory structures. Practical solutions for 4 K × 9 bits and 16 K × 1 bit memories are given.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced MOSFET technologies: A review 先进的MOSFET技术综述
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469254
J. Borel
{"title":"Advanced MOSFET technologies: A review","authors":"J. Borel","doi":"10.1109/ESSCIRC.1976.5469254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469254","url":null,"abstract":"","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115989070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信