D. Keymeulen, A. Stoica, R. Zebulum, Y. Jin, V. Duong
{"title":"Fault-tolerant approaches based on evolvable hardware and using a reconfigurable electronic devices","authors":"D. Keymeulen, A. Stoica, R. Zebulum, Y. Jin, V. Duong","doi":"10.1109/IRWS.2000.911896","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911896","url":null,"abstract":"The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics. The fitness approach defines, in an explicit way, the faults that the component may encounter during its life time and evaluates the average behavior of the individuals. The population approach uses the implicit information of the population statistics accumulated by the genetic algorithm over many generations. The paper presents experiments done using both approaches on a fine-grained CMOS Field Programmable Transistor Array (FPTA) architecture for the synthesis of a fault-tolerant XNOR digital circuit. Experiments show that the evolutionary algorithm is able to find a fault-tolerant design for the XNOR function that can recover functionality when lost due to not a-priori known faults, by finding new circuits configurations that circumvent the faults. Our preliminary experiments show that the population approach designs a fault-tolerant circuit with a better performance and in less computation than the fitness based approach.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127492242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of short-time classical HC stresses for in-line reliability control of sub-0.5 /spl mu/m nMOSFETs","authors":"R. Gonella","doi":"10.1109/IRWS.2000.911925","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911925","url":null,"abstract":"The purpose of this paper is to show that in advanced sub-0.5 /spl mu/m technologies, short-time classical hot-carrier (HC) stress tests are suitable for a predictive in-line monitoring. The ability of such tests in detecting maverick lots and the comparison with the performances of an already proposed fast method, lead to consider this approach as very attractive for wafer-level reliability control (WLRC) purposes.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel electrical test to differentiate gate-to-source/drain silicide short from gate oxide short","authors":"A. Yassine, K. Wieczorek, K. Olasupo, V. Heinig","doi":"10.1109/IRWS.2000.911907","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911907","url":null,"abstract":"A novel method that differentiates gate oxide failures from silicide bridging between gate and source/drain is presented. The method can be incorporated into Voltage Ramp Dielectric Breakdown test (VRDB) or as a stand-alone test to detect silicide bridging. It requires the test structure to have gate, source/drain and well terminals. The gate and substrate currents must be monitored during the test at a low gate voltage in accumulation mode. This method uses two criteria, one for the gate current, Ig, and one for the well (substrate) current, Iw. The silicide short was initially simulated by connecting a shunt resistor between the gate and the drain of the device. Actual data are also presented for MOS devices with silicide bridging along with TEM cross-sections.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128578912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Schafft, L. Head, J. Lechner, J. Gill, T. Sullivan
{"title":"Deep-censoring method for early reliability assessment","authors":"H. Schafft, L. Head, J. Lechner, J. Gill, T. Sullivan","doi":"10.1109/IRWS.2000.911890","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911890","url":null,"abstract":"Deep censoring is proposed as a direct method to assess the early reliability of semiconductor products. The method characterizes, in particular, the early part of the failure-time distribution and is described in the context of interconnect reliability and electromigration. In this context, it involves stressing a large number of test lines only long enough for some small number of lines to fail, enough to characterize the percentiles of the failure-time distribution that are of interest. Simulations and other calculations show that this approach offers the benefits of much reduced test times and better confidence in sample estimates of early percentiles and of sigma. It can also be used to detect and characterize extrinsic failure-time distributions. An experimental approach is proposed that uses special test structures with many parallel-running test lines. This makes possible early reliability assessments at the wafer level with a full-wafer testing system.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128447580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An improved substrate current model for deep submicron CMOS transistors","authors":"Wei Li, J. Yuan, S. Chetlur, J. Zhou, A. Oates","doi":"10.1109/IRWS.2000.911924","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911924","url":null,"abstract":"A simple and accurate substrate current model was developed by modifying the model of ionization characteristic length and tested for both n-channel and p-channel devices against the measurement data. It shows a better match by comparing with other models reported in the literature. The model has been used to simulate the transient substrate current in circuit operating conditions to show its ability to predict the device and circuit lifetime.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability issues of ultra-thick gate oxides","authors":"U. Schwalke, M. Polzl, T. Sekinger, M. Kerber","doi":"10.1109/IRWS.2000.911923","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911923","url":null,"abstract":"In this work, degradation and breakdown characteristics of ultra-thick gate oxides (Tox: 50 nm-120 nm) used in power MOS devices is investigated. Measurements indicate, that the established thin-oxide models for lifetime extrapolations from accelerated tests may not be appropriate for ultra-thick oxides and lead to erroneous results.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electromigration discussion group summary moderators","authors":"H. Schafft, T. Sullivan","doi":"10.1109/IRWS.2000.911916","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911916","url":null,"abstract":"","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121356643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Lanchava, P. Baumgartner, A. Martin, A. Beyer, E. Mueller
{"title":"Comparison of two standard WLR current-ramped tests for oxide reliability","authors":"B. Lanchava, P. Baumgartner, A. Martin, A. Beyer, E. Mueller","doi":"10.1109/IRWS.2000.911936","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911936","url":null,"abstract":"A comparison between the GOX-Reliability results obtained on 7.5 nm and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms-a CSQ (Current Step Qbd) stress on the one hand and the JEDEC J-Ramp, on the other hand-are presented. The observed influence of the ramping profile and the step holding time t/sub step/ on the reliability data shows a strong dependence on the type of device under test (DUT). The P-type MOS-devices seem to be more susceptible to the changes of the current ramping rate. The obtained results are discussed in terms of the GOX interface roughness, depletion effects during the stress, and the serial resistance of the test structure.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132659487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Kelsey-Wynne, F. Chen, J. Furukawa, T. Sullivan
{"title":"Characterization of extrusion formation during high temperature anneal","authors":"J. Kelsey-Wynne, F. Chen, J. Furukawa, T. Sullivan","doi":"10.1109/IRWS.2000.911929","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911929","url":null,"abstract":"Stress relaxation in aluminum-copper (Al-Cu) films at elevated temperatures can result in problematic extrusion formation. Extrusions in Al-Cu lines can potentially grow towards neighboring lines and short devices, resulting in reliability and product yield concerns. Improved understanding of the driving mechanisms behind extrusion formation is necessary to quantify the contribution of different variables for better process window control. Scanning electron microscopy was used to view the extrusions that form along the sides of metal lines before oxide deposition. A kinetics study was performed on various metal stacks and metal line dimensions in addition to a comparison study of standard anneal and rapid thermal anneal processes. The results of these studies were analyzed and compared with a model assuming diffusion based growth as well as with a finite element model.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quasi-breakdown in ultra-thin oxides: some insights on the physical mechanisms","authors":"S. Bruyère, D. Roy, E. Vincent, G. Ghibaudo","doi":"10.1109/IRWS.2000.911898","DOIUrl":"https://doi.org/10.1109/IRWS.2000.911898","url":null,"abstract":"This paper discusses the variation of the probability to observe quasi-breakdown with capacitor topology and stress conditions and gets some insights on the physical mechanisms of both breakdown and quasi-breakdown phenomena. To achieve this goal, a methodology based on competing mechanisms between breakdown and quasi-breakdown is introduced in order to rigorously analyze Time Dependent Dielectric Quasi-breakdown. This approach is found to provide specific and distinct parameters for breakdown and quasi-breakdown, such as Weibull slope, acceleration factor and activation energy, which enable to well model the quasi-breakdown rate behavior with the capacitor topology and the stress conditions. This good adequation first validate this methodology and undoubtedly indicates that the physical defects at the origin of both phenomena are different. Additionally, the quasi-breakdown is demonstrated to occur on a reduced window of carrier energy, what confirms the distinct origins of both phenomena. Moreover, this induces some important consequences concerning reliability extrapolation, since the critical failure mode can be different at high field than at nominal condition.","PeriodicalId":374889,"journal":{"name":"2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}