Implementation of short-time classical HC stresses for in-line reliability control of sub-0.5 /spl mu/m nMOSFETs

Abstract

The purpose of this paper is to show that in advanced sub-0.5 /spl mu/m technologies, short-time classical hot-carrier (HC) stress tests are suitable for a predictive in-line monitoring. The ability of such tests in detecting maverick lots and the comparison with the performances of an already proposed fast method, lead to consider this approach as very attractive for wafer-level reliability control (WLRC) purposes.