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2018 International Symposium on Devices, Circuits and Systems (ISDCS)最新文献

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A RISC-V ISA compatible processor IP for SoC SoC的RISC-V ISA兼容处理器IP
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379629
Suseela Budi, Pradeep Gupta, Kuruvilla Varghese, Amrutur Bharadwaj
{"title":"A RISC-V ISA compatible processor IP for SoC","authors":"Suseela Budi, Pradeep Gupta, Kuruvilla Varghese, Amrutur Bharadwaj","doi":"10.1109/ISDCS.2018.8379629","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379629","url":null,"abstract":"The emergence of System-on-Chip technology has brought in opportunities in the form of reduced cycle time, superior performance and time-to-market considerations. Our work focusses on a new processor for a System on Chip. The system has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART. The processor is based on RISC-V ISA. It supports Integer, Multiply, and Atomic instructions. Memory subsystem includes split caches and translation lookaside buffers. Interrupt controller supports four levels of preemptive priority and preemption can be programmed for individual interrupts. Memory error control module provides single error correction and double error detection for main memory. Wishbone B.3 bus standard is adopted as on-chip bus protocol. The design is implemented on Virtex-7 (XC7VX485tffg1761-2) board and achieves a peak clock frequency of 100MHz.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116071613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Modeling of multi-dimensional system and its application for robot development 多维系统建模及其在机器人开发中的应用
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379643
T. Maiti, Y. Ochi, M. Miura-Mattausch, D. Navarro, H. Mattausch
{"title":"Modeling of multi-dimensional system and its application for robot development","authors":"T. Maiti, Y. Ochi, M. Miura-Mattausch, D. Navarro, H. Mattausch","doi":"10.1109/ISDCS.2018.8379643","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379643","url":null,"abstract":"In this presentation, our achievement on multi-dimensional system modeling and its application for robot development are discussed. The model considers multi-dimensional aspect of robot-system simulation, characterized by the nature of both Cartesian and polar systems kinematics. Thus model includes electro-mechanical coupling behavior sensor (e.g., pressures sensor) and actuator (e.g., servo motor) in addition to the electrical coupling for the robot control. The electro-mechanical coupling of a sensor is confined to two-dimensional spaces which are structural and electric fields that handle its kinematic behaviour in Cartesian coordinate system. The actuator electro-mechanical coupling combines the electrical and rotational kinematic by preserving energy conservation relation between electrical and mechanical domains. The rotational kinematic quantities of servo-motor such as shaft angle, velocity, acceleration and torque are implemented in polar coordinate system. We demonstrate a robot-system simulation with the developed model to improve the motion of a walking robot.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of CMOS based Class-A Power Amplifier for C-Band applications 基于CMOS的c波段a类功率放大器设计
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379625
Priti Gupta, Nigidita Pradhan, S. K. Jana
{"title":"Design of CMOS based Class-A Power Amplifier for C-Band applications","authors":"Priti Gupta, Nigidita Pradhan, S. K. Jana","doi":"10.1109/ISDCS.2018.8379625","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379625","url":null,"abstract":"This work presents the design of 8 GHZ CMOS based Class-A Power Amplifier (PA) with synthesized Transformer Matching Network (TMNs). The circuit is implemented in 180nm process technology using semiconductor laboratory Process Design KIT(SCL PDKs). Transformer based Matching Network is used to provide matching at the output side of the C-Band ∼ 8GHz class-A power amplifier. The optimized simulated results shows that power added efficiency is 22.74 %, power gain is 32.77 dBm, total harmonic distortion (THD) is 11.40 %, Compression Point 1.77 dBmand IPN Curves2.016 dBm. This optimized results can be used in transreceiver for High speed communication systems.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"33 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123468041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Introduction to dielectrically modulated biological field effect transistor 介质调制生物场效应晶体管简介
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379627
S. Kanungo
{"title":"Introduction to dielectrically modulated biological field effect transistor","authors":"S. Kanungo","doi":"10.1109/ISDCS.2018.8379627","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379627","url":null,"abstract":"In this embedded tutorial, a comprehensive account of dielectrically modulated biological field effect transistor (DM-BioFET) has been presented. The tutorial offers a general overview on BioFET, indicating the underlying physics of charge-modulated and dielectric-modulated transduction mechanism. Next, gradual developments in DM-BioFET have been discussed, and the effects of device downscaling on transduction performance has been typically emphasized. Subsequently, different DM-BioFET designs for transducer performance optimization has been analyzed from their device electrostatics and carrier transport mechanism. The comparative merits/ demerits of such emerging variants of DM-BioFET are also indicated in this context. In essence, the tutorial attempted to convey a clear understanding of DM-BioFET based biosensors for general readers, and the present research scenario, future promises as well as research challenges of this domain are duly elaborated for interested researchers.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127718361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ARDUINO UNO based packed U cell inverter for photovoltaic application 基于ARDUINO UNO的光伏应用封装U单元逆变器
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379633
T. Bhattacharya, P. Sarkar
{"title":"ARDUINO UNO based packed U cell inverter for photovoltaic application","authors":"T. Bhattacharya, P. Sarkar","doi":"10.1109/ISDCS.2018.8379633","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379633","url":null,"abstract":"In the area of renewable energy uses, multilevel inverter still remain a subject matter for research and development to reduce its circuit complexity. Packed U Cell (PUC) multilevel inverter is a recent variant, extensively being used in photovoltaic applications as an alternative to meet the shortage in power demands focusing too much on decreasing the installation cost, increase system's efficiency, reliability and modularity. It is important to act to decrease this cost through designing a power conditioning circuit with lower cost. To meet this objective ARDUINO UNO is used in generating and providing pulse width modulated (PWM) signals to control the gates of Insulated Gate Bipolar Transistor (IGBT) that constitute the major building block of PUC multilevel inverter. MATLAB/Simulink is used in development of the photovoltaic system which includes PV modules, Maximum Power Point Tracking (MPPT) controller, DC-DC boost converter and PUC inverter. The simulation result validate the merits and performance of this proposed scheme.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124387761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel reversible synthesis of array multiplier 一种新的可逆阵列乘法器合成方法
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379667
D. Kole, H. Rahaman, D. K. Das, Somnath Rakshit, Sraboni Mondal
{"title":"A novel reversible synthesis of array multiplier","authors":"D. Kole, H. Rahaman, D. K. Das, Somnath Rakshit, Sraboni Mondal","doi":"10.1109/ISDCS.2018.8379667","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379667","url":null,"abstract":"Quantum computation has seen immense progress which has popularised logic synthesis with the help of reversible circuits. A reversible circuit is implemented with multiple special types of quantum gates, known as k-CNOT gates. Ion trapping or nuclear magnetic resonance are newer technologies required to emulate quantum gates. This paper presents a reversible synthesis of array multipliers based on Booths Algorithm implemented with reversible k-CNOT gates. Our work has been simulated using the online quantum simulator davyw and its features have been compared with existing reversible array multipliers.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116995221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of electron beam dose for reliable nanoscale growth template formation in electron beam lithography system 电子束光刻系统中可靠的纳米级生长模板生成的电子束剂量优化
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379635
S. Guhathakurata, S. Chattopadhyay, M. Palit
{"title":"Optimization of electron beam dose for reliable nanoscale growth template formation in electron beam lithography system","authors":"S. Guhathakurata, S. Chattopadhyay, M. Palit","doi":"10.1109/ISDCS.2018.8379635","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379635","url":null,"abstract":"Dose optimization of electron beam has been performed for transferring nano-dimension patterns by employing electron beam lithography. An extensive study has been conducted for optimizing lithographic features with e-beam resist PMMA of different thicknesses. It has been possible to obtain sub-80 nm circular dot patterns with good resolution and high aspect ratio. Au template has been developed by employing lift-off technique for subsequent nanostructure growth employing VLS method. TiO2 nanoislands have been grown on patterned Au template and its crystallographic nature has been studied by using X-ray diffraction measurement. The grown nanoislands showed perfect hexagonal facets.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123126558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparative investigation of Ga- and Sn-doped ZnO nanowires/p-Si heterojunctions for UV-photo sensing Ga和sn掺杂ZnO纳米线/p-Si异质结用于紫外光传感的比较研究
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379683
R. Saha, A. Karmakar, S. Chattopadhyay
{"title":"Comparative investigation of Ga- and Sn-doped ZnO nanowires/p-Si heterojunctions for UV-photo sensing","authors":"R. Saha, A. Karmakar, S. Chattopadhyay","doi":"10.1109/ISDCS.2018.8379683","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379683","url":null,"abstract":"Vertically oriented undoped, Ga-doped and Sn-doped ZnO nanowires are grown by using novel double step chemical bath deposition (CBD) technique. The nanowire morphology, crystallite quality, energy bandgap, and UV-visible absorption properties are investigated by employing FESEM, XRD and UV-vis measurements. Comparative photoresponse of the ZnO nanowire/p-Si heterojunction photodiodes is studied by measuring the photo-to-dark current ratios, self-powered photo-switching behavior and intensity-dependant photocurrent at zero applied bias. Ga-doped ZnO nanowires/p-Si heterojunction photodiode exhibits relatively higher photocurrent while the Sn-doped devices show faster photoswitching operation. An excellent photoresponse with the linear dependency of photocurrent on the incident UV-intensity has been observed in the Sn-doped photodiodes.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128846449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Steiner tree construction for graphene nanoribbon based circuits in presence of obstacles 存在障碍物的石墨烯纳米带电路的斯坦纳树结构
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379664
Subrata Das, D. K. Das
{"title":"Steiner tree construction for graphene nanoribbon based circuits in presence of obstacles","authors":"Subrata Das, D. K. Das","doi":"10.1109/ISDCS.2018.8379664","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379664","url":null,"abstract":"For special geometric structure, graphene nanoribbon based interconnect can be bent only in 0°, 60° and 120° angles. Hence the underlying routing grid of graphene nanoribbon based circuits and interconnects are aligned to these mentioned degrees only. Such a routing grid is known as triangular routing grid. In the routing paths of graphene nanoribbon based inter-connects some hexagonal obstacles may be present there due to some pre-existing routing paths or due to some other reasons. For a given source, a set of n sink terminals and a set of obstacles in a triangular grid we have to interconnect the source and the sink terminals avoiding the obstacles in such a way that hybrid cost is minimized. Here the interconnect cost due to length and bending is known as hybrid cost. In this paper, we propose an algorithm for the construction of obstacles-avoiding hexagonal steiner tree for graphene nanoribbon based circuits. The algorithm is tested in a random data set and the experimental results are quite encouraging.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"45 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123407988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Soft fault detection in analog circuits from probability density function 基于概率密度函数的模拟电路软故障检测
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-29 DOI: 10.1109/ISDCS.2018.8379676
S. Srimani, K. Ghosh, H. Rahaman
{"title":"Soft fault detection in analog circuits from probability density function","authors":"S. Srimani, K. Ghosh, H. Rahaman","doi":"10.1109/ISDCS.2018.8379676","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379676","url":null,"abstract":"A new parametric fault detection scheme for linear and weakly non-linear analog circuits is proposed from probability density function (PDF) of the output. Non-parametric kernel density estimation (KDE) technique is used to estimate the PDF from the random output of the circuit excited with random input stimuli. Two benchmark circuits viz. Continuous-time low pass State Variable Filter circuit and Cascade Amplifier are tested to validate the proposed framework. All the circuits are simulated with CADENCE Virtuoso using UMC-180nm technology. Detectability of the proposed method of soft fault detection is appreciably higher than that of functional test method.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126012680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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