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2008 4th Southern Conference on Programmable Logic最新文献

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Reconfigurable Architecture for Embedding Web Services 嵌入Web服务的可重构架构
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547742
S. Cuenca-Asensi, H. Ramos-Morillo, F. Maciá-Pérez
{"title":"Reconfigurable Architecture for Embedding Web Services","authors":"S. Cuenca-Asensi, H. Ramos-Morillo, F. Maciá-Pérez","doi":"10.1109/SPL.2008.4547742","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547742","url":null,"abstract":"The Web services framework is specially conceived for integrating, in an easy way, different internet services from different providers. Web services have been widely adopted in business applications using PC-based servers as their main implementation platform. However, the nowadays growing computational and communication power of the FPGA devices allows its implementation taking advantage of the special features that those platforms offer. In this work we propose a reconfigurable architecture to support web services that reduces the cost and maintenance of the system and increases the security and robustness of the service. The feasibility of our approach is demonstrated by developing a specific service, called WoLI, which allows the remote wake up of network nodes over internet. The prototype has been proved and tested in a real environment where the service is accessible from any client able to support standard communication with a Web server.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131584407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Polynomic Curve based Representation System Implemented using FPGAs 用fpga实现的多项式曲线表示系统
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547736
C. Piñeiro, C. Valbuena, H. Mecha
{"title":"Polynomic Curve based Representation System Implemented using FPGAs","authors":"C. Piñeiro, C. Valbuena, H. Mecha","doi":"10.1109/SPL.2008.4547736","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547736","url":null,"abstract":"A polynomic curve based representation system is a three-dimensional system for rendering images using polynomic curves instead of triangles meshes. This system allows render a scene in a way that the computational cost depends on the image size more than on the scene complexity. Moreover, It allows the user to describe a scene using a minimal amount of data in comparison with traditional methods. According to that, we have implemented a hardware that demonstrates how this kind of applications can be accelerated in a huge grade using the proper solution. The hardware was implemented on a FPGA; thanks to it, the execution times were very reduced, showing a very promising speedup compared against an only software solution.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Radiation Hardening of FPGA-Based SoCs through Self-Reconfiguration and XTMR Techniques 基于fpga的soc的自重构和XTMR技术的辐射硬化
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547772
A. Martín-Ortega, Maite Alvarez, S. Esteve, Santiago Rodriguez, Sergio Lopez-Buedo
{"title":"Radiation Hardening of FPGA-Based SoCs through Self-Reconfiguration and XTMR Techniques","authors":"A. Martín-Ortega, Maite Alvarez, S. Esteve, Santiago Rodriguez, Sergio Lopez-Buedo","doi":"10.1109/SPL.2008.4547772","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547772","url":null,"abstract":"SRAM-based FPGAs are increasingly being used in space applications. However, there are still many concerns about the reliability of these devices in high-radiation environments, particularly due to the possibility of single-event upsets (SEUs) in the configuration memory. This paper presents an architecture for implementing radiation-hardened SoCs based on FPGAs. Previous works used triple module redundancy (TMR) techniques together with scrubbing mechanisms based on partial reconfiguration. However, these solutions required external configuration controllers that increased the system complexity and deviated the design from the SoC principles. The proposed architecture uses novel self- reconfiguration techniques in order to eliminate the need for external components, so that a full radiation-hardened SoC can be implemented in a single FPGA. Since self- reconfiguration allows for on-board remote hardware updates, reliability is tackled at two key levels: Radiation- hardened operation and hardware upgradeability to solve design errors.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123524350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Aerodynamics Analysis Acceleration through Reconfigurable Hardware 通过可重构硬件进行空气动力学分析加速
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547740
E. Andrés, M. Molina, G. Botella, A. D. Del Barrio, J. Mendias
{"title":"Aerodynamics Analysis Acceleration through Reconfigurable Hardware","authors":"E. Andrés, M. Molina, G. Botella, A. D. Del Barrio, J. Mendias","doi":"10.1109/SPL.2008.4547740","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547740","url":null,"abstract":"The long computation times required to simulate complete aircraft configurations remain as the main bottleneck in the design flow of new structures for the aeronautics industry. In this paper, the novel application of specific hardware in conjunction with conventional processors to accelerate Computational fluid dynamics is explored. First, some general facts about application-specific hardware are presented, placing the focus on the feasibility of the development of hardware modules (FPGAs based) for the acceleration of most time-consuming algorithms in aeronautics analysis. So, a practical methodology for developing an FPGA- based computing solution for the quasi ID Euler equations is applied to the Sod's \"shock tube\" problem. Results comparing CPU-based and FPGA-based solutions are presented, showing that speedups around two orders of magnitude can be expected from the FPGA-based implementation.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132864874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
TDES Implementation in a Reconfigurable Computing Enviroment 可重构计算环境中的TDES实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547755
J.A. Jaramillo-Villegas, E.M. Correa-Agudelo, R. Gomez-Londono
{"title":"TDES Implementation in a Reconfigurable Computing Enviroment","authors":"J.A. Jaramillo-Villegas, E.M. Correa-Agudelo, R. Gomez-Londono","doi":"10.1109/SPL.2008.4547755","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547755","url":null,"abstract":"The objective of this project is to evaluate the performance of the algorithm TDES (Triple Data Encryption Standard), used for encryption on high speed Ethernet networks. The algorithm is implemented using a hardware acceleration methodology in a reconfigurable computing environment, through a hardware description language, referred as VHDL (very high speed integrated circuit hardware description language), based in a FPGA (field programmable gate array). The results of the evaluation will be compared with results of the test done over a traditional software solution implemented by OpenSSL. It will be possible with the comparison to determine which solution has the best performance.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Elliptic-Curve Point-Multiplication over GF(2163) GF(2163)上的椭圆曲线点乘法
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547727
J. Deschamps, G. Sutter
{"title":"Elliptic-Curve Point-Multiplication over GF(2163)","authors":"J. Deschamps, G. Sutter","doi":"10.1109/SPL.2008.4547727","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547727","url":null,"abstract":"This paper describes algorithms and circuits for executing the point-multiplication operation in the particular case of the K-163 NIST-recommended curve. The circuits have been described in VHDL and implemented within the low cost Spartan-3 FPGA devices. Three point-multiplication algorithms are considered: the basic algorithm, the Montgomery algorithm and an algorithm based on the Frobenius map.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130472292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synthesis of Low-Power Synchronous Controllers using FPGA Implementation 基于FPGA的低功耗同步控制器合成实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547762
D. L. Oliveira, A.F.T. Salazar, L. Romano
{"title":"Synthesis of Low-Power Synchronous Controllers using FPGA Implementation","authors":"D. L. Oliveira, A.F.T. Salazar, L. Romano","doi":"10.1109/SPL.2008.4547762","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547762","url":null,"abstract":"Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the low- consumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"387 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection 用于HDL IP核心保护的组合逻辑模式中的自动签名插入
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547753
Encarnación Castillo, L. Parrilla, Antonio García, Uwe Meyer-Baese, Guillermo Botella, A. Lloris
{"title":"Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection","authors":"Encarnación Castillo, L. Parrilla, Antonio García, Uwe Meyer-Baese, Guillermo Botella, A. Lloris","doi":"10.1109/SPL.2008.4547753","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547753","url":null,"abstract":"This paper presents significant improvements to previous watermarking technique for intellectual property protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting that, in addition to easy the signature hosting, leads to reduced area penalties. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116537183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Architectural Tradeoffs in the Design of Barrel Shifters for Reconfigurable Computing 面向可重构计算的桶形移位器设计中的架构权衡
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547728
H. Neto, M. Véstias
{"title":"Architectural Tradeoffs in the Design of Barrel Shifters for Reconfigurable Computing","authors":"H. Neto, M. Véstias","doi":"10.1109/SPL.2008.4547728","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547728","url":null,"abstract":"Barrel shifters are utilized by special and general-purpose arithmetic units to manipulate data. Several types of shifting operations exist depending on the target application, including shift logical, shift arithmetic and rotate. In this work a set of hardware design alternatives for shifters to perform the different types of shifting operations was analyzed, designed and implemented in a Virtex-4- FPGA. The results show that several implementations with different trade-offs between performance and area can be obtained and that high throughput can be achieved using pipelining techniques.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121303844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding MP3译码多相滤波器组的硬件实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547726
M. Valdés, M. J. Moure, J. Diéguez, S. Antelo
{"title":"Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding","authors":"M. Valdés, M. J. Moure, J. Diéguez, S. Antelo","doi":"10.1109/SPL.2008.4547726","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547726","url":null,"abstract":"MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera's Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage of its architecture oriented to DSP applications. DSP Builder design tools have been used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123889726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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