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2008 4th Southern Conference on Programmable Logic最新文献

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Energy Evaluation in the Nios II Processor as a Function of Cache Sizes 作为缓存大小函数的Nios II处理器中的能量评估
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547732
D. M. Cambre, E. Boemo, E. Todorovich
{"title":"Energy Evaluation in the Nios II Processor as a Function of Cache Sizes","authors":"D. M. Cambre, E. Boemo, E. Todorovich","doi":"10.1109/SPL.2008.4547732","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547732","url":null,"abstract":"This paper is a study of the Nios II power characterization. The relationship between instruction and data cache sizes and the corresponding energy consumption is analyzed. The study is based on more than one thousand current measurements for different benchmark programs and cache configurations. From the results it is clear that using the optimal cache sizes leads to the lowest energy consumption even when considering execution time, power, and FPGA resources utilization. As an additional result the paper shows an example where the use of integer instead of floating point operations can save a significant amount of energy. Lastly, it is shown that the energy consumption as a function of the input data size follows the same function as the computational complexity for the studied examples.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114981252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units 嵌入式浮点运算单元fpga中的粗粒度/细粒度逻辑接口
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1155/2008/736203
Chi Wai Yu, J. Lamoureux, S. Wilton, P. Leong, W. Luk
{"title":"The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units","authors":"Chi Wai Yu, J. Lamoureux, S. Wilton, P. Leong, W. Luk","doi":"10.1155/2008/736203","DOIUrl":"https://doi.org/10.1155/2008/736203","url":null,"abstract":"This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. The results show that (1) FPUs should be square, (2) FPUs should be positioned tightly near the center of the FPGA and (3) that the FPU pins should be arranged on four sides of the FPU.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
FPGA-Based Transmit/Receive Distributed Controller for the TR Modules of an L Band Antenna (SAR) 基于fpga的L波段天线TR模块收发分布式控制器
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547744
J. Siman, G. Jaquenod, H. Mascialino
{"title":"FPGA-Based Transmit/Receive Distributed Controller for the TR Modules of an L Band Antenna (SAR)","authors":"J. Siman, G. Jaquenod, H. Mascialino","doi":"10.1109/SPL.2008.4547744","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547744","url":null,"abstract":"A synthetic aperture radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. The SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. This paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. This device was chosen after evaluation of SRAM, FLASH and antifuse technologies , and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"74 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114251736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Complete Emulation System for Single Event Effects Analysis 一个完整的单事件效应分析仿真系统
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547760
J. Napoles, H. Guzmán-Miranda, M. Aguirre, J. Tombs, J. M. Mogollón, R. Palomo, A. P. Vega-Leal
{"title":"A Complete Emulation System for Single Event Effects Analysis","authors":"J. Napoles, H. Guzmán-Miranda, M. Aguirre, J. Tombs, J. M. Mogollón, R. Palomo, A. P. Vega-Leal","doi":"10.1109/SPL.2008.4547760","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547760","url":null,"abstract":"Trends show that next coming technologies will produce new generations of very large circuits, running at high clock rates. Some critical applications will have to be protected against the remaining radiation at sea level. This is especially important in aerospace applications because ionizing radiation produces corruption of the internal state. New design methods have to be introduced to assure circuits will tolerate the impact of single event effects (SEE). It is very important to be able to analyze which parts of the circuits are more critical and how the behavior of the global system is degraded when one part suffers a SEE. This paper presents the last functionalities added to the FT-UNSHADES system to extend the analysis to SETs and MBUs. As a result, the system can insert and analyze many fault types at a rate of 180 K faults per hour in a system with 2 million test vectors.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114068707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low Cost FPGA based USB Device Core 基于FPGA的低成本USB设备核心
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547747
E.A.A. De Maria, E. Gho, C.E. Maidana, F.I. Szklanny, H.R. Tantignone
{"title":"A Low Cost FPGA based USB Device Core","authors":"E.A.A. De Maria, E. Gho, C.E. Maidana, F.I. Szklanny, H.R. Tantignone","doi":"10.1109/SPL.2008.4547747","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547747","url":null,"abstract":"The universal serial bus (USB) standard has become, in recent years, an important product for use in digital communications, as a direct replacement for different communication interfaces previously used with relevant advantages. Because of this, there are increasing needs for systems implementations to include the USB communication standard in a variety of applications. In order to solve this challenge, this paper introduces a low cost USB core, developed to address a variety of applications using FPGA integrated circuits.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116238961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Function Call Optimisation in SystemC Hardware Compilation SystemC硬件编译中的函数调用优化
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547738
J. Ditmar, S. McKeever
{"title":"Function Call Optimisation in SystemC Hardware Compilation","authors":"J. Ditmar, S. McKeever","doi":"10.1109/SPL.2008.4547738","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547738","url":null,"abstract":"Functions are commonly used in SystemC and other high-level languages to divide code into separate tasks. During synthesis, a hardware compiler can instantiate logic for each function call. Alternatively, a function can be mapped to a separate piece of hardware that is shared between calls to the function. This process, called function exlining, can significantly improve logic usage of a design. This paper investigates the benefits of function exlining in hardware compilation and proposes a method for implementing this optimisation in SystemC. In this method, exlining is described as a source transformation which can be easily implemented in existing compiler frameworks. The method has been implemented in a commercial SystemC hardware compiler and experiments show that exlining function calls can significantly reduce the logic size of a design.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126404781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies FFT/IFFT模块在FPGA上的实现:方法比较
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547724
J. Viejo, A. Millán, M. Bellido, E. Ostúa, P. Ruiz-de-Clavijo, A. Muñoz
{"title":"Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies","authors":"J. Viejo, A. Millán, M. Bellido, E. Ostúa, P. Ruiz-de-Clavijo, A. Muñoz","doi":"10.1109/SPL.2008.4547724","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547724","url":null,"abstract":"In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Image Processing Architecture to Exploit I/O Bandwidth on Reconfigurable Computers 一种利用可重构计算机I/O带宽的图像处理体系结构
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547771
Miaoqing Huang, O. Serres, Sergio Lopez-Buedo, Tarek El-Ghazawi, Greg Newby
{"title":"An Image Processing Architecture to Exploit I/O Bandwidth on Reconfigurable Computers","authors":"Miaoqing Huang, O. Serres, Sergio Lopez-Buedo, Tarek El-Ghazawi, Greg Newby","doi":"10.1109/SPL.2008.4547771","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547771","url":null,"abstract":"FPGA devices in reconfigurable computers (RCs) allow datapath, memory, and processing elements (PEs) to be customized in order to achieve very efficient algorithm implementations. However, the maximum speedup on RCs is bounded by the bandwidth available between muPs and FPGA hardware accelerators. In this paper, an image processing architecture is presented to fully exploit this bandwidth for achieving the maximum possible speedup. This architecture can be used to implement any convolution operation between an image and a kernel, and comprises four fully pipelined components: a line buffer, a data window, an array of PEs and a data concatenating block. Multiple image processing algorithms have been successfully implemented using this architecture, such as digital filters, edge detectors, and image transforms. In all cases, the maximum throughput is upper-bounded by the muP-FPGA I/O bandwidth, regardless of the complexity of the algorithm. This end-to-end throughput has been measured to be 1.2 GB/s on Cray XD1 and 2.1 GB/s on SGI RC100.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133925955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Control Unit for a Motion Detector based on Histograms 一种基于直方图的运动检测器控制单元
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547757
V.O. Roda, D.C.R. Minhoni
{"title":"A Control Unit for a Motion Detector based on Histograms","authors":"V.O. Roda, D.C.R. Minhoni","doi":"10.1109/SPL.2008.4547757","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547757","url":null,"abstract":"A motion detector system searches in a sequence of video frames for information that reveals movement on the monitored scene. Motion detection can be used in many applications such as for surveillance, human motion analysis, vehicle and pedestrian detection and tracking and in robotics. A motion detection system based on histograms was developed. The system acquires and digitizes video frames from a video camera and stores the digitized data in RAM memory. The digitized pixel data is integrated on the horizontal and vertical directions providing the respective horizontal and vertical histograms. The histograms can be compared frame to frame and when a movement occurs in the scene, a noticeable difference on the histograms will appear on the correspondent spatial region of the image. In this paper we present the control unit for the developed motion detector.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128866436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated Hardware/Software Codesign for Heterogeneous Computing Systems 异构计算系统的集成软硬件协同设计
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547761
Y. Lam, J. Coutinho, W. Luk
{"title":"Integrated Hardware/Software Codesign for Heterogeneous Computing Systems","authors":"Y. Lam, J. Coutinho, W. Luk","doi":"10.1109/SPL.2008.4547761","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547761","url":null,"abstract":"This paper describes a strategy that integrates the task mapping and task scheduling steps for heuristic search techniques, with multiple neighbourhood functions to reduce search time and enchance solution quality in developing heterogeneous computing systems. For case studies involving 40 randomly generated task graphs and the fast Fourier transform, experimental results show that our approach outperfroms previous approaches in terms of search time by up to 93 times, and solution quality by up to 22.6% for a system with a microprocessor, a floating-point digital signal processor, and an FPGA.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133737861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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