Energy Evaluation in the Nios II Processor as a Function of Cache Sizes

Abstract

This paper is a study of the Nios II power characterization. The relationship between instruction and data cache sizes and the corresponding energy consumption is analyzed. The study is based on more than one thousand current measurements for different benchmark programs and cache configurations. From the results it is clear that using the optimal cache sizes leads to the lowest energy consumption even when considering execution time, power, and FPGA resources utilization. As an additional result the paper shows an example where the use of integer instead of floating point operations can save a significant amount of energy. Lastly, it is shown that the energy consumption as a function of the input data size follows the same function as the computational complexity for the studied examples.