{"title":"基于fpga的L波段天线TR模块收发分布式控制器","authors":"J. Siman, G. Jaquenod, H. Mascialino","doi":"10.1109/SPL.2008.4547744","DOIUrl":null,"url":null,"abstract":"A synthetic aperture radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. The SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. This paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. This device was chosen after evaluation of SRAM, FLASH and antifuse technologies , and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"74 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"FPGA-Based Transmit/Receive Distributed Controller for the TR Modules of an L Band Antenna (SAR)\",\"authors\":\"J. Siman, G. Jaquenod, H. Mascialino\",\"doi\":\"10.1109/SPL.2008.4547744\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A synthetic aperture radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. The SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. This paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. This device was chosen after evaluation of SRAM, FLASH and antifuse technologies , and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.\",\"PeriodicalId\":372678,\"journal\":{\"name\":\"2008 4th Southern Conference on Programmable Logic\",\"volume\":\"74 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 4th Southern Conference on Programmable Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2008.4547744\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 4th Southern Conference on Programmable Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2008.4547744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA-Based Transmit/Receive Distributed Controller for the TR Modules of an L Band Antenna (SAR)
A synthetic aperture radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. The SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. This paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. This device was chosen after evaluation of SRAM, FLASH and antifuse technologies , and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.