Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Abstract

Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the low- consumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.