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2008 4th Southern Conference on Programmable Logic最新文献

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An Efficient Fault Simulator for QDI Asynchronous Circuits 一种高效的QDI异步电路故障模拟器
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547739
A. Rahmani, Ali-Asghar Salehpour, S. Mohammadi, H. Pedram
{"title":"An Efficient Fault Simulator for QDI Asynchronous Circuits","authors":"A. Rahmani, Ali-Asghar Salehpour, S. Mohammadi, H. Pedram","doi":"10.1109/SPL.2008.4547739","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547739","url":null,"abstract":"Testing asynchronous circuits is a difficult task because of two main reasons; first, the absence of a global clock does not allow the use of traditional test generation techniques used for synchronous circuits. Second, correct (i.e., hazard- free) operations of asynchronous circuits are usually obtained by introducing redundancies, that is, sacrificing the testability. So test frameworks such as fault simulator for synchronous circuits are not applicable for asynchronous circuits. In this paper we present an efficient fault simulator for template-based asynchronous circuits which is based on checking sequence of signals in templates. Our proposed fault simulator provides higher fault coverage by taking into consideration the detection of a special class of faults called premature firing faults without introducing any hardware redundancy in the designed circuit. Experimental results on a set of circuits have shown the effectiveness of the fault simulator.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power Savings in FPGA Video Compression Systems through Intra Prediction Result Reuse 基于帧内预测结果复用的FPGA视频压缩系统节能研究
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547749
G. Stewart, D. Renshaw, M. Riley
{"title":"Power Savings in FPGA Video Compression Systems through Intra Prediction Result Reuse","authors":"G. Stewart, D. Renshaw, M. Riley","doi":"10.1109/SPL.2008.4547749","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547749","url":null,"abstract":"A novel algorithm is proposed to reduce the power used performing the motion estimation and reference frame loading operations required by a video encoder. The algorithm uses the results of the intra prediction encoding stage to determine the data propagation direction which minimises the data's transition activity. A motion estimation architecture which can adaptively change the direction data is propagated through it is proposed and the power saved using the algorithm is estimated. Results are given showing a power saving of upto 8%.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Real Time FPGA based Thresholding Segmentation in a Multi Touch System 基于FPGA的实时阈值分割在多点触摸系统中的应用
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547766
E.A.A. De Maria, E. Gho, C.E. Maidana, C. Rodriguez, F.I. Szklanny, H.R. Tantignone
{"title":"Real Time FPGA based Thresholding Segmentation in a Multi Touch System","authors":"E.A.A. De Maria, E. Gho, C.E. Maidana, C. Rodriguez, F.I. Szklanny, H.R. Tantignone","doi":"10.1109/SPL.2008.4547766","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547766","url":null,"abstract":"The main objective of the interface controller depicted in this paper is to improve data capture from a multi touch interface based on FTIR (frustrated-total-internal-reflection) techniques, applying thresholding methods for image segmentation. In order to arrive to this goal, a FPGA based controller has been developed, which will be able to process a video signal in real time, thus allowing data to be extracted into a computer system for different applications. This controller also allows full system calibration, based on a real time histogram generator, which forms part of the developed system.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124631509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Architecture of FDP FPGA Device FDP FPGA器件的结构
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547734
Jinmei Lai, Liguang Chen, Rui Tu, Man Wang, Yuan-Gang Wang, J. Tong, Yabin Wang, Huowen Zhang
{"title":"The Architecture of FDP FPGA Device","authors":"Jinmei Lai, Liguang Chen, Rui Tu, Man Wang, Yuan-Gang Wang, J. Tong, Yabin Wang, Huowen Zhang","doi":"10.1109/SPL.2008.4547734","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547734","url":null,"abstract":"A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131202499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel Implementation of the Shortest Path Algorithm on FPGA 最短路径算法的FPGA并行实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547768
I. Fernandez, J. Castillo, C. Pedraza, C. Sánchez, J.I. Martinez
{"title":"Parallel Implementation of the Shortest Path Algorithm on FPGA","authors":"I. Fernandez, J. Castillo, C. Pedraza, C. Sánchez, J.I. Martinez","doi":"10.1109/SPL.2008.4547768","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547768","url":null,"abstract":"An implementation of a parallel version of the shortest path algorithm on a Virtex-II Pro FPGA device that computes the minimal distance in a graph in a more efficiently way than the classical algorithms is presented The paper shows how the hardware/software codesign process is applied in order to design the system using a PowerPC processor running Linux on a XUP Virtex-II Pro development board. The coprocessor's hardware architecture is fully described as well as the software running in Linux that is in charge of transferring data between the host computer, the PPC and the application-specific coprocessor. The synthesis results are presented as well as a comparative study of speedups for the parallel and the sequential implementation of the algorithm, showing a good improvement from the presented version against a software version running in a PC.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131220303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
SSDR - Reconfigurable Firewall: Reconfiguration Model Performance SSDR -可重构防火墙:可重构模型性能
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547770
F. D. Pereira, E.D.M. Ordonez
{"title":"SSDR - Reconfigurable Firewall: Reconfiguration Model Performance","authors":"F. D. Pereira, E.D.M. Ordonez","doi":"10.1109/SPL.2008.4547770","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547770","url":null,"abstract":"There are a number of techniques and pieces of hardware and software aimed at promoting information security. In the present paper it is presented a security system dynamically reconfigurable in FPGAs. SSDR presents a robust architecture, which enables the implementation of specific and general security policies in order to guarantee services such as confidentiality, authenticity, integrity, availability, access control, and information audit. The main purposes of SSDR include guaranteeing a great security level by reaching time performance acceptable to a conventional computer network, besides a greater flexibility in relation to a configuration of functionalities and to the security policies. In this paper it presented the reconfigurable firewall module, highlighting its architecture, functionalities and performance, as well as focusing on the impact on the reconfigurable time according the model of project adopted.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132289399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FPGA based Multi-Harmonic Control System for Single Bubble Sonoluminescence 基于FPGA的单泡声致发光多谐波控制系统
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547774
D. Dellavale, M. O. Sonnaillon, F. Bonetto
{"title":"FPGA based Multi-Harmonic Control System for Single Bubble Sonoluminescence","authors":"D. Dellavale, M. O. Sonnaillon, F. Bonetto","doi":"10.1109/SPL.2008.4547774","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547774","url":null,"abstract":"An integrated multi-harmonic control system based on field programmable gate array (FPGA) technology is developed in this article. The system was designed to generate a controlled multi-harmonic excitation for a non linear phenomenon: single bubble sonoluminescence (SBSL). The target excitation for our experiment is constituted by a set of senoidal signals, the fundamental frequency and several harmonic frequencies. The FPGA device allowed the customized implementation and successfully integrated all the design requests in a single board. On line control over the largest number of harmonics ever reported in the literature is provided by the developed system. Experimental results show the integrated system performance.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125759181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Reconfigurable Prototyping Platform for Smart Sensor Networks 智能传感器网络的可重构原型平台
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547743
H. Hinkelmann, A. Reinhardt, S. Varyani, M. Glesner
{"title":"A Reconfigurable Prototyping Platform for Smart Sensor Networks","authors":"H. Hinkelmann, A. Reinhardt, S. Varyani, M. Glesner","doi":"10.1109/SPL.2008.4547743","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547743","url":null,"abstract":"In this paper, a new concept for a very flexible and modular prototype platform for rapid prototyping of wireless sensor networks is presented. We propose to use a FPGA with high gate count as core of the platform. The FPGA is utilized to attain 3 major goals for the prototype platform: to emulate arbitrary mote architectures even including smart motes with high system complexity, to realize flexible interfaces to sensors and radio transceivers, and to embed versatile debugging and system monitoring functionality in the mote prototypes. The presented prototype platform is suitable to realize complete sensor networks based on different mote architectures, different wireless communication schemes, and arbitrary application domains. The design concepts and implementation aspects of the platform are presented and discussed in detail.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126901736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
FPGA based Architecture for Robust Optical Flow Computation 基于FPGA的鲁棒光流计算架构
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547723
G. Botella, E. Ros, M. Rodriguez, A. García, E. Andrés, M. Molina, E. Castillo, L. Parrillcra
{"title":"FPGA based Architecture for Robust Optical Flow Computation","authors":"G. Botella, E. Ros, M. Rodriguez, A. García, E. Andrés, M. Molina, E. Castillo, L. Parrillcra","doi":"10.1109/SPL.2008.4547723","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547723","url":null,"abstract":"Motion Computation, also called Optical Flow, consists of measuring the motion of an entity attending to the modulus (how fast) and the phase (direction) of its movement. There are a plethora of different models and algorithms whereas none of them cover all problems associated to the real world. Our contribution presents a novel customizable architecture, including resource usage and performance, of a neuromorphic robust optical flow adjustable platform, although its main drawback is the elevated computational complexity. Bioinspiration and robustness properties of the final system provides an extended set of applications fields.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA Implementation of an Adaptive Noise Canceller for Robust Speech Enhancement Interfaces 鲁棒语音增强接口自适应消噪器的FPGA实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547725
V. Rodellar, A. Álvarez, C. Conzalez, P. Gómez, E. Martinez
{"title":"FPGA Implementation of an Adaptive Noise Canceller for Robust Speech Enhancement Interfaces","authors":"V. Rodellar, A. Álvarez, C. Conzalez, P. Gómez, E. Martinez","doi":"10.1109/SPL.2008.4547725","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547725","url":null,"abstract":"This paper describes the design and implementation results of an adaptive Noise canceller useful for the construction of robust speech enhancement interfaces. The algorithm being used has very good performance for real time applications. Its main disadvantage is the requirement of calculating several operations of division, having a high computational cost. Besides that, the accuracy of the algorithm is critical in fixed-point representation due to the wide range of the upper and lower bounds of the variables implied in the algorithm. To solve this problem, the accuracy is studied and according to the results obtained a specific word-length has been adopted for each variable. The algorithm has been implemented for Altera and Xilinx FPGAs using high level synthesis tools. The results for a fixed format of 40 bits for all the variables and for a specific word-length for each variable are analyzed and discussed.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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