The Architecture of FDP FPGA Device

Jinmei Lai, Liguang Chen, Rui Tu, Man Wang, Yuan-Gang Wang, J. Tong, Yabin Wang, Huowen Zhang
{"title":"The Architecture of FDP FPGA Device","authors":"Jinmei Lai, Liguang Chen, Rui Tu, Man Wang, Yuan-Gang Wang, J. Tong, Yabin Wang, Huowen Zhang","doi":"10.1109/SPL.2008.4547734","DOIUrl":null,"url":null,"abstract":"A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 4th Southern Conference on Programmable Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2008.4547734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.
FDP FPGA器件的结构
提出了一种新的复旦可编程(FDP) FPGA器件结构。与传统的4输入LUT相比,新的基于3-LUT的逻辑单元可以增加约11%的逻辑密度。独特的分层可编程布线结构和有效的开关箱可以优化布线线段,使不同长度的布线线段直接高效连接成为可能。FDP FPGA器件包含1,600个可编程逻辑单元,160个可编程IO块和16 K位双端口块RAM IP核。采用中芯国际0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V工艺制造,芯片尺寸为6.1 × 6.6 mm2,封装为QFP208。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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