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2008 4th Southern Conference on Programmable Logic最新文献

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Design of a Mathematical Unit in FPGAs for the Implementation of the Control of a System of Magnetic Levitation 实现磁悬浮系统控制的fpga数学单元设计
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547729
J. J. Raygoza-Panduro, S. Ortega-Cisneros, J. Rivera, A. de la Mora
{"title":"Design of a Mathematical Unit in FPGAs for the Implementation of the Control of a System of Magnetic Levitation","authors":"J. J. Raygoza-Panduro, S. Ortega-Cisneros, J. Rivera, A. de la Mora","doi":"10.1109/SPL.2008.4547729","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547729","url":null,"abstract":"This paper presents the design and implementation of a mathematical unit, which is generated automatically, from a program elaborated in Java that describes the circuit in VHDL, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as: mathematical functions including; sine, cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of system is used in industrial applications requiring high level mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper the results of the mathematical core are shown in terms of implementation, utilization and application to control a magnetic levitation system.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"13 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133043127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A VHDL CAN Module for Smart Sensors 智能传感器的VHDL CAN模块
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547752
J.E.O. Reges, Edval J. P. Santos
{"title":"A VHDL CAN Module for Smart Sensors","authors":"J.E.O. Reges, Edval J. P. Santos","doi":"10.1109/SPL.2008.4547752","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547752","url":null,"abstract":"Communication modules are required for smart sensors interface with the sensor network. In this paper, a VHDL (VHSIC hardware description language) implementation of a CAN (controller area network) interface for smart sensors is presented. The scope of this paper is the medium access control (MAC) sublayer. Therefore, it deals with the transfer protocol, control of frames, arbitration, error checking and error signaling. In accordance with the CAN protocol (versions 2.0 A and 2.0 B), the interface can be divided into blocks to perform various communication tasks. In the implementation presented in this work, each block is a VHDL project entity described in the behavioral style. The performance of each entity is analyzed separately. Next, all entities are interconnected in the structural style. The final description has been synthesized into a Xilinxreg Spartan-Il XC2S50 FPGA. Finally, a comparison between this implementation and the HurriCANe, a freely available core, is performed.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115163270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Iddt Test Calibration using a Programmable Processing Array 使用可编程处理阵列的Iddt测试校准
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547773
M. Itskovich, J. Plusquellic
{"title":"Iddt Test Calibration using a Programmable Processing Array","authors":"M. Itskovich, J. Plusquellic","doi":"10.1109/SPL.2008.4547773","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547773","url":null,"abstract":"This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300 kHz, independently of vector size.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128408855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hazard-Free Implementation of the Extended Burst-Mode Asynchronous Controllers in Look-Up Table based FPGA 基于FPGA的查找表扩展突发模式异步控制器的无害化实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547746
Duarte L. Oliveira, S. S. Sato, O. Saotome, R. T. D. Carvalho
{"title":"Hazard-Free Implementation of the Extended Burst-Mode Asynchronous Controllers in Look-Up Table based FPGA","authors":"Duarte L. Oliveira, S. S. Sato, O. Saotome, R. T. D. Carvalho","doi":"10.1109/SPL.2008.4547746","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547746","url":null,"abstract":"FPGAs have been mainly used for design of synchronous circuits. It is, however, difficult to design asynchronous circuits on them because the circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as extended burst- mode, on FPGAs based on look-up table architectures. We state a sufficient condition so the implementation in FPGAs becomes essential hazard-free. By doing that, asynchronous circuits, besides their intrinsic advantages over synchronous ones, may also take advantage of integration, lower costs and design short-time associated with FPGA designs.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134544640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A VLSI Architecture Suitable for Mid-Level Image Processing 一种适合中级图像处理的VLSI架构
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547737
G. Dessbesell, M.A. Pacheco, J.B. dos S. Martins, R.F. Molz
{"title":"A VLSI Architecture Suitable for Mid-Level Image Processing","authors":"G. Dessbesell, M.A. Pacheco, J.B. dos S. Martins, R.F. Molz","doi":"10.1109/SPL.2008.4547737","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547737","url":null,"abstract":"Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123553667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Digital PLL Circuit for AC Power Lines with Instantaneous Sine and Cosine Computation 一种具有瞬时正弦余弦计算的交流电源线数字锁相环电路
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547731
R. Cayssials, O. Alimenti, E. Ferro
{"title":"A Digital PLL Circuit for AC Power Lines with Instantaneous Sine and Cosine Computation","authors":"R. Cayssials, O. Alimenti, E. Ferro","doi":"10.1109/SPL.2008.4547731","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547731","url":null,"abstract":"In this paper we propose a digital architecture to implement a PLL for a sinusoidal analog input. This kind of components is intended for synchronization between the voltage (current) of a AC power line and a voltage (current) synthesized by a converter. The architecture is based on binary-rate multiplers modules and generates the sine and the cosine values of the sinusoidal input reference. Most of PLLs implemented for those applications utilise analog components whose performance are mainly limited by power supply noise coupling. Besides, they require calibrations to avoid precision errors. Our approach proposes a fully digital implementation of a PLL and consequently it is immune to most of the interferences and calibrating errors of analog PLLs. Experimental and theoretical results conclude that the architecture proposed could be suitable for most of the applications where this kind of PLLs is applied.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125557459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a Wireless Control System with Self Timed Activation for Mobile Robots 移动机器人自定时激活无线控制系统的实现
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547758
S. Ortega-Cisneros, J. J. Raygoza-Panduro, A. de la Mora, O. Castillo
{"title":"Implementation of a Wireless Control System with Self Timed Activation for Mobile Robots","authors":"S. Ortega-Cisneros, J. J. Raygoza-Panduro, A. de la Mora, O. Castillo","doi":"10.1109/SPL.2008.4547758","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547758","url":null,"abstract":"This work presents the implementation of a wireless system for the control of mobile robots using circuits with Self-Timed (ST) Synchronization, implemented in reconfigurable devices FPGAs. The system is composed of a global network of small ST processors, which will develop independent processes communicated by means of modules of wireless transmission that form the network of activation of peripheral units. The proposal of this project consists of developing a wireless network of processors with fixed stations and mobiles, designed to low power by means of the use of circuits with Self-Timed synchronization. Every station of transmission consists in a ST microprocessor and a Xbee transmitter that transmits in a wireless way the instructions to the robot.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FastCam: Real-Time Implementation of the Lucky Imaging Technique using FPGA FastCam:利用FPGA实现的幸运成像技术
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547748
J. Piqueras, L. Rodríguez-Ramos, Y. Martín, J. J. Martínez-Álvarez
{"title":"FastCam: Real-Time Implementation of the Lucky Imaging Technique using FPGA","authors":"J. Piqueras, L. Rodríguez-Ramos, Y. Martín, J. J. Martínez-Álvarez","doi":"10.1109/SPL.2008.4547748","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547748","url":null,"abstract":"FastCam project combines the features of the lucky imaging technique for astronomical imaging through the Earth's atmosphere, with the real-time processing capabilities of re- configurable logic. An acquisition, processing and communication system based exclusively on reconfigurable hardware has been developed and tested at laboratory and telescopes. The proposed approach uses FPGAs and their natural parallel arrangements to achieve a just one chip implementation of the whole system. Exceptional both astronomical and technological results have been obtained by using the instrument in real medium- sized telescopes. As for FPGAs, the robust, versatile and high speed architecture built shows that this technology is not only a viable solution but probably also the best one. Regarding astronomy, the spatial resolution of the telescopes has been enhanced to their diffraction limit, obtaining clear benefit from the real-time display of the processed images.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115225013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core 基于Microblaze软核的嵌入式应用程序数字数据处理外设设计
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547756
E. Ostúa, J. Viejo, M. Bellido, A. Millán, J. Juan, A. Muñoz
{"title":"Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core","authors":"E. Ostúa, J. Viejo, M. Bellido, A. Millán, J. Juan, A. Muñoz","doi":"10.1109/SPL.2008.4547756","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547756","url":null,"abstract":"In this paper we present a design of a peripheral for microblaze soft core processor as part of a R+D project carried out in cooperation with three different companies. The objective of the project consisted in the development of an embedded system with a SoC implemented on a FPGA custom-designed board. This work addresses the design of a digital data processing peripheral included as a part of the target SoC application, that process digital signals via the digital inputs on a proposed board. Peripheral functionality is configurable for each digital signal independently and is configured from the software running on the microblaze processor core.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132405128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On the Reconfiguration Costs of Models for Partially Reconfigurable FPGAs 部分可重构fpga模型的重构代价研究
2008 4th Southern Conference on Programmable Logic Pub Date : 2008-03-26 DOI: 10.1109/SPL.2008.4547741
S. Lange, M. Middendorf
{"title":"On the Reconfiguration Costs of Models for Partially Reconfigurable FPGAs","authors":"S. Lange, M. Middendorf","doi":"10.1109/SPL.2008.4547741","DOIUrl":"https://doi.org/10.1109/SPL.2008.4547741","url":null,"abstract":"There exists several FPGA architectures that can be partially reconfigured at run-time. The advantage of partial run-time reconfiguration is that it allows to develop new algorithmic solutions for many applications. But a limiting factor for using frequent dynamic reconfiguration could be the reconfiguration overhead. In order to study the potential of frequent run-time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. In this paper, we provide a formal treatment of the reconfiguration costs and compare them for models of standard partially reconfigurable FPGAs and 2-level reconfigurable FPGAs.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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