{"title":"MP3译码多相滤波器组的硬件实现","authors":"M. Valdés, M. J. Moure, J. Diéguez, S. Antelo","doi":"10.1109/SPL.2008.4547726","DOIUrl":null,"url":null,"abstract":"MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera's Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage of its architecture oriented to DSP applications. DSP Builder design tools have been used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.","PeriodicalId":372678,"journal":{"name":"2008 4th Southern Conference on Programmable Logic","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding\",\"authors\":\"M. Valdés, M. J. Moure, J. Diéguez, S. Antelo\",\"doi\":\"10.1109/SPL.2008.4547726\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera's Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage of its architecture oriented to DSP applications. DSP Builder design tools have been used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.\",\"PeriodicalId\":372678,\"journal\":{\"name\":\"2008 4th Southern Conference on Programmable Logic\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 4th Southern Conference on Programmable Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2008.4547726\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 4th Southern Conference on Programmable Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2008.4547726","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding
MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera's Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage of its architecture oriented to DSP applications. DSP Builder design tools have been used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.
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