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2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)最新文献

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Structure preserving modeling for safety critical systems 安全关键系统的结构保持建模
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177866
G. Uygur, S. Sattler
{"title":"Structure preserving modeling for safety critical systems","authors":"G. Uygur, S. Sattler","doi":"10.1109/IMS3TW.2015.7177866","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177866","url":null,"abstract":"To warrant the functionality of safety critical circuits and systems, underlying functions have to be modeled in a fashion that preserves real-world structure. That means, it must be ensured that the formally derived functions of the real-world structure should be in consistent conformance with the functions generated by the structure itself. Conversely, from safety-related aspects, it is fatal, when the modeled functions behave different from their functions in reality. Thus, although structure preserving modeling is safety-relevant, the state of the art does not consistently handle the formal derivation and modeling of functions. Particularly this happens at asynchronous feedbacked structures, especially in favor of simplification and later optimization. Looking at a very elementary asynchronous feedback logic, we show that this problem of inconsistency is omnipresent, and that our demand for consistency can not be warranted by the state of the art methods. We propose a new modeling methodology that is capable to preserve the structure of asynchronous feedback.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128297502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Digital on-chip measurement circuit for built-in phase noise testing 内置相位噪声测试的数字片上测量电路
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177880
S. David-Grignot, F. Azais, L. Latorre, F. Lefèvre
{"title":"Digital on-chip measurement circuit for built-in phase noise testing","authors":"S. David-Grignot, F. Azais, L. Latorre, F. Lefèvre","doi":"10.1109/IMS3TW.2015.7177880","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177880","url":null,"abstract":"This paper presents a digital on-chip measurement circuit for built-in phase noise evaluation of analog/IF signals. The technique relies on 1-bit acquisition and on-the-fly processing to compute a digital signature related to the phase noise level present in the analog signal. In order to minimize the required hardware resources, the circuit is designed with a semipipeline architecture and modular arithmetic. It has been implemented for validation on a FPGA-based platform. Experimental measurements on both a synthesized signal and the IF output of a silicon tuner demonstrate a very good agreement with the conventional external technique.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"780 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of an on-chip stepwise ramp generator for ADC static BIST applications 用于ADC静态BIST应用的片上阶跃斜坡发生器设计
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177876
G. Renaud, M. Barragán, S. Mir
{"title":"Design of an on-chip stepwise ramp generator for ADC static BIST applications","authors":"G. Renaud, M. Barragán, S. Mir","doi":"10.1109/IMS3TW.2015.7177876","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177876","url":null,"abstract":"This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124714408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Automated triangular wave generator design with process corners compensation 自动三角波发生器设计，工艺角补偿
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177883
Yasser Moursy, R. Iskander, M. Louerat
{"title":"Automated triangular wave generator design with process corners compensation","authors":"Yasser Moursy, R. Iskander, M. Louerat","doi":"10.1109/IMS3TW.2015.7177883","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177883","url":null,"abstract":"In this paper, a systematic design methodology is proposed to design a triangular wave generator circuit. Using this methodology, various oscillation frequencies can be obtained in a shorter design time. Furthermore, the variations in the oscillation frequency are controlled across all process corners. The proposed methodology employs a transistor sizing and biasing CAD tool called CHAMS, in which the sizes and biases of each transistor are performed to meet the required DC operating points. Across all process corners, the error in the oscillation frequency can be controlled by changing the trimming current. Simulations across nine corners are done to estimate the error in frequency. The condition to pass the design is to guarantee that for each process corner, at least one of the trimming combination sets the oscillation frequency within the specified limits. The methodology is applied for different arbitrary values of frequencies 1 MHz, 2 MHz, and 4 MHz with a maximum error of ±3%.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ACR BER correlation to ATE for a COFDM VHF RX COFDM VHF RX的ACR BER与ATE的相关性
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177861
Peter Sarson
{"title":"ACR BER correlation to ATE for a COFDM VHF RX","authors":"Peter Sarson","doi":"10.1109/IMS3TW.2015.7177861","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177861","url":null,"abstract":"With a BER to SNR correlation, it was found that it was possible to test ACR in VHF receivers with one measurement. Moving component testing for any device from the bench to ATE poses many challenges, but releasing a high-speed RF device with a design margin issue to a production setting is somewhat challenging. To facilitate the testing of ACR in a production environment, a technique was found that correlated ACR in terms of BER to SNR. This technique, which was developed for ATE, also greatly reduced test time whilst ensuring highly reliable test results.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Timing measurement BOST with multi-bit delta-sigma TDC 时序测量BOST与多位δ σ TDC
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177881
Takeshi Chujo, D. Hirabayashi, Takuya Arafune, S. Shibuya, Shu Sasaki, Haruo Kobayashi, Masanobu Tsuji, Ryoji Shiota, Masafumi Watanabe, N. Dobashi, Sadayoshi Umeda, Hideyuki Nakamura, Koshi Sato
{"title":"Timing measurement BOST with multi-bit delta-sigma TDC","authors":"Takeshi Chujo, D. Hirabayashi, Takuya Arafune, S. Shibuya, Shu Sasaki, Haruo Kobayashi, Masanobu Tsuji, Ryoji Shiota, Masafumi Watanabe, N. Dobashi, Sadayoshi Umeda, Hideyuki Nakamura, Koshi Sato","doi":"10.1109/IMS3TW.2015.7177881","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177881","url":null,"abstract":"This paper describes design and implementation of a multi-bit delta-sigma (ΔΣ) Time-to-Digital Converter (TDC) with Data-Weighted-Averaging (DWA) algorithm on analog FPGA. I/O interfacing circuits such as double-data-rate (DDR) memory interfaces are very important, and their low-cost, high-quality test is challenging. We propose here simple test circuitry for measuring digital signal timing of I/O interfacing circuits with high resolution and good accuracy. We focus on TDC applications of ΔΣmodulators (for fine-timing-resolution, digital output, and simple circuitry) and with multi-bit architecture (for short testing time). However, the multi-bit ΔΣ TDC suffers from delay mismatches among delay cells. Then we propose to apply the DWA algorithm for the delay cells in order to solve this problem. Our experimental results showed that the DWA algorithm improved the overall multi-bitΔΣ TDC linearity.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121217362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Using IJTAG digital islands in analogue circuits to perform trim and test functions 在模拟电路中使用IJTAG数字岛来执行微调和测试功能
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177859
H. M. von Staudt, A. Spyronasios
{"title":"Using IJTAG digital islands in analogue circuits to perform trim and test functions","authors":"H. M. von Staudt, A. Spyronasios","doi":"10.1109/IMS3TW.2015.7177859","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177859","url":null,"abstract":"Demand for analogue precision and accuracy has significantly increased over the last few years, way beyond what the foundries can produce. At the same time short design cycles require the addition of digital configuration, trim, or assist functions to compensate for variation and uncertainties. Favourable configurations and trim values are then stored on chip in fuse arrays or OTP (One Time Programmable) as part of the test program. While such digital assist functions are generally viewed as cheap this is not necessarily the case in analogue heavy processes (130/180/250 nm). An additional constraint is the minimalistic digital interface to the tester, which is usually just an I2C interface. In this paper a scheme is described which utilises the recently introduced IJTAG standard (IEEE 1687) in an industrial environment. It allows the creation of digital islands close to the analogue circuit with minimal digital overhead. These IJTAG islands can hold the test and trim functions, which are distinct from the customer oriented use case. The mapping between I2C and IJTAG is transparent for the existing legacy test software and for the initialisation state machine which transfers the configuration and trim data from a central fuse or OTP block.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An approach to generate test signals for analog circuits — A control-theoretic perspective 生成模拟电路测试信号的一种方法——控制理论的观点
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177868
W. Vermeiren, Fabian Hopsch, R. Jancke
{"title":"An approach to generate test signals for analog circuits — A control-theoretic perspective","authors":"W. Vermeiren, Fabian Hopsch, R. Jancke","doi":"10.1109/IMS3TW.2015.7177868","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177868","url":null,"abstract":"This paper presents a control-theoretic driven approach to the automatic generation of test signals for analog circuits or systems. It is based on the adaption of a tracking control structure for the task of generating test signals aimed at manufacturing test for a finished circuit design. The approach will be derived and its functionality is demonstrated using circuit examples. The integration of the proposed approach within a more general test development procedure for improving the fault coverage is explained.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123597071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling static analog behavior for determining mixed-signal test coverage using digital tools 建模静态模拟行为确定混合信号测试覆盖使用数字工具
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177869
C. Wegener
{"title":"Modeling static analog behavior for determining mixed-signal test coverage using digital tools","authors":"C. Wegener","doi":"10.1109/IMS3TW.2015.7177869","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177869","url":null,"abstract":"Determining test coverage for digital circuits is a commercially solved problem. This solution enables Design-forTest (DfT) which is justified by the increase in test coverage achieved. Applying digital tools to analog and mixed-signal circuits requires modeling analog circuit behavior. By representing single-wire analog behavior using a digital bus, the multi-level nature of analog signals can be “understood” by the digital tool. Using test coverage as a metric, mixed-signal DfT can be applied and justified. In this contribution, we consider the example of a Successive Approximation Register (SAR) ADC, comprising a digital controller and an analog feedback loop. This mixed-signal circuit is modeled such that a standard digital tool can be applied for determining test coverage and even generating test patterns. By adding DfT, i.e. additional controllability and observability, we can demonstrate improved test coverage. This improvement can be weighted against the additional silicon expense and ultimately justifies the DfT applied.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121144117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of stress acceleration on mixed-signal gate oxide lifetime 应力加速度对混合信号栅极氧化物寿命的影响
2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW) Pub Date : 2015-06-24 DOI: 10.1109/IMS3TW.2015.7177872
Kexin Yang, L. Milor
{"title":"Impact of stress acceleration on mixed-signal gate oxide lifetime","authors":"Kexin Yang, L. Milor","doi":"10.1109/IMS3TW.2015.7177872","DOIUrl":"https://doi.org/10.1109/IMS3TW.2015.7177872","url":null,"abstract":"A methodology to estimate the lifetime due to gate oxide breakdown (GOBD) is presented. The results of this analysis show that devices in analog circuits experience unequal stress acceleration and this impacts lifetime estimates at use conditions and can cause some devices to fail relatively more frequently under accelerated conditions in comparison with use conditions. We calculate the impact of voltage and temperature acceleration on circuits by combining the impact of voltage and temperature acceleration on each device to find the circuit-level acceleration factors. Because the acceleration factors are not constant for analog circuits, we propose to use reliability simulation to properly estimate acceleration factors under the uneven stress conditions experienced by mixed-signal circuits. The acceleration factors can then be used to estimate circuit lifetime at use conditions, given empirical data on failure rates of chips at high temperature and voltage stress conditions.","PeriodicalId":370144,"journal":{"name":"2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115470205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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