Design of an on-chip stepwise ramp generator for ADC static BIST applications

Abstract

This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.